512位元RSA公匙加解密晶片之設計與研製

512-bit RSA Public Key Data Encryption/Decryption Chip Design

葉碧青(Bih-Ching Yeh)

指導教授 ： 吳紹懋

元智大學/工程學院/電機與資訊工程研究所/碩士(1997年)

摘要

摘 要

本文中我們研製了一個512位元以RSA演算法為基礎的公匙加解密器.
設計此晶片的目的是為了增加網路資料傳輸的安全性.電路設計為四階式
管線式架構(Four-Stage)以提昇加解密的速度. 簡而言之,此晶片設計的
重點在於有效率地計算Y = XE mod N的指數與模運算,其中參數X, E與N為
512位元.我們引用了指數運算演算法和Montgomery演算法來簡化複雜的指
數運算單元的設計.
所設計的RSA晶片由模擬的數據可得, 其完成一次n位元的RSA加密或解
密運算需花費大約1.5n2時脈週期, 以512位元來說, 加密或解密運算需花
費大約1.5*5122個時脈週期.
晶片時脈頻率可達100MHz, 加解密的速度可達到每秒193K位元, 功率
消耗約為420mW.

關鍵字

公匙 ； 加解密 ； 管線式

並列摘要

ABSTRACT

In this thesis we design a chip intended to support fast
execution of the RSA public-key cryptographic algorithm. The
goal to design this chip is to increase the security of data
transmission in the network. In order to speed up the encryption
or decryption throughput, we use the four-stage pipeline to
design our circuits. Generally speaking, the chip is designed
to efficiently calculate the modular power function
( Y = XE mod N ), where the parameters X, E and N up to 512 bits
long . We reference both of the Exponential Modulus algorithm
and Montgomery's algorithm to simplify the complexity of
Exponential Modulus unit design.
The simulation results show that it takes about 1.5n2 clock
cycles to finish one n-bit RSA encryption(decryption)operation.
That's to say, if n is 512 then it needs about 1.5*5122 clock
cycles to finish one 512-bit RSA encryption (decryption)
operation. Our 512-bit RSA chip can operate up to 100Mhz,
allowing an encryption (decryption) speed up to 193k bits/sec
and the power consumption is 420mW.

並列關鍵字

RSA ； Montgomery ； encryption ； decryption ； public key ； pipeline

參考文獻

[1] Bruce Schneier, Applied Cryptography : Protocols,

Algorithms, and Source Code in C, John Wiley & Sons, Inc., 1994.

[2] Charles P. Pfleeger, Security in Computing, Prentice Hall

International Editions, 1997.

[3] M. Shand and J. Vuillemin, "Fast Implementations of RSA