以FPGA實現可部份重組化架構的嵌入式系統

Using FPGA Implement a Partial Reconfigurable Architecture of Embedded System

張友青(Y.C. Chang)

指導教授 ： 黃朝章

元智大學/資訊學院/資訊工程學系/碩士(2004年)

摘要

現今的科技日新月異，資訊產品均以輕薄短小為訴求，於是在單一晶片上完成所有的設計已經成為了趨勢，嵌入式系統正可謂之代表。且面對規格多變、多樣化產品不斷出現的今天，如何延長產品在市場上的存活時間，獲得更多利潤成為一個重要的課題。
於是，本論文提出一個可部份重組化架構的嵌入式系統，這個系統主要結合了一個軟體可程式化的主要中央處理器以及一個或多個可重組化單元，利用FPGA（Field Programmable Gate Array）可程式化的特性，我們能夠依照需求的特定功能來重新組態可重組化單元，改變硬體架構以滿足各種不同的應用，也可藉由硬體快速處理的能力提昇效能。這種介於ASIC（Application Specific Integrated Circuit）與GPP（General-Purpose Processor）之間的形態極有可能成為一個最佳化的系統架構。

關鍵字

嵌入式系統 ； 可重組 ； FPGA

並列摘要

The science and technology changes with each passing day, information products be required with light and thin, hence completing all designs at single chip become a trend, the embedded system is typical example. Today the specification of products are changeful and variety. How to lengthen the lifetime on the market of products and obtaining more profits becomes an important issue.
The thesis proposes a partial reconfigurable architecture of embedded system, the system combine one major MPU (MicroProcessor unit) and many reconfigurable units. Utilize the characteristic of FPGA (Field Programmable Gate Array), we could reconfigure the reconfigurable unit according to demand for specific function and change the architecture of hardware to satisfy different kinds of application. In addition, it can also promote compute efficiency by hardware circuit. Therefore, this architecture is most probably become an optimization system between ASIC (Application Specific Integrated Circuit) and GPP (General-Purpose Processor).

並列關鍵字

Embedded System ； Reconfigurable ； FPGA

參考文獻

[1] Xilinx, Inc. MicroBlaze Processor Reference Guide, August 12, 2003.

[6] Sakho. Design and Implement of Dynamic Reconfigurable Architecture Base on Embedded System, July 23, 2004.

[7] Xilinx, Inc. Embedded System Tools Reference Guide, January 30, 2004.

[10] Xilinx, Inc. User Core Templates Reference Guide, January, 2004.

[2] E. L. Horta and J. W. Lockwood. PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGA). Technical report, Department of Computer Science, Applied Research Lab, Washington University, Saint Louis, July 2001.