不同到達時間的多元輸入訊號覆疊之元件時序特性化

Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times

董慧香(Hui-Hsiang Tung)

指導教授 ： 林榮彬

元智大學/工程學院/電機與資訊工程研究所/碩士(1997年)

摘要

在高速VLSI設計上，時序預算（timing budget）通常都是很吃緊且需要更精確的時序分析（timing analysis），因此，元件時序特性化的準確度有進一步加強的必要。其中方法之一是從事多元輸入元件（cell with multiple inputs）時序延遲的特性化。如果我們在決定輸出反應，同時考慮到所有輸入對輸出的影響，就能增進時序特性化的準確度。本論文針對多元輸入元件時序延遲特性化提出一解決方法。這個方法把所有對輸出反應有影響的輸入之波形斜率, 輸入之不同到達時間及輸出負載等因素納入考慮。應用本論文提出的方法，我們設計了一個初級的多元輸入延遲邏輯模擬器 ( preliminary multiple-delay logic simulator)，其所產生之時序資料以HSPICE模擬驗證，誤差範圍皆在±10%以內。

關鍵字

多元輸入 ； 時序特性化 ； 不同到達時間 ； 時序分析 ； 多元輸入訊號覆疊 ； 元件時序特性化

並列摘要

For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider simultaneously all the inputs that will influence the output response. In this thesis we propose an approach to timing characterization of a multi-input gate. The approach would consider input slopes, output load and arrival times of all the inputs that influence the output response. A preliminary multiple-delay logic simulator is designed based on the proposed approach. The timing delay produced by the multiple-delay logic simulator is within ±10% of that obtained by HSPICE simulation.

並列關鍵字

multiple inputs ； timing characterization ； different arrival times ； timing analysis ； multiple input transitions ； timing characterization of gate delay

參考文獻

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