使用CPLD建構IDEA加密及解密晶片研究設計

The Research and Design for a High Performance Encryption and Decryption Chip Using Complex Programmable Logic Device

王增智(Tseng-Chih Wang)

指導教授 ： 黃朝章

元智大學/工程學院/電機與資訊工程研究所/碩士(1997年)

摘要

本論文研製之IDEA(International Data Encryption Algorithm)加密及解密晶片，是一種以加密金匙長度為128個位元的密鑰；將64位元的明文(Plain text)區塊，配合128個位元所產生出來的52把16位元的密鑰；經過八個回合(8-rounds)連續加密運算後產生出64位元的密文(Cipher text)區塊。在每個回合運算處理中，經由混合「以位元為單位的Exclusive-OR」、「216的模加法運算」、「(216 + 1) 的模乘法運算」三種核心運算函數而成。 IDEA演算法於1992年公布至今仍然未見有密文被破解的文獻發表，由此可見此一演算法確實具有相當高的安全性。

因此，在本論文之研究中我們選擇了IDEA做為設計加密、解密晶片的核心演算法；此外，為了滿足在不同應用環境中的不同需求，我們採用模組化的設計架構：將每兩個回合的加密及解密運算整合在一個晶片中，使得系統應用及處理器的控制介面更有彈性，在效能加強方面：我們提出以管線式平行化處理的IDEA核心演算法硬體架構，以解決因為資料相依之故而無法進行運算資料平行化處理的問題。如此，才能使預期的系統執行效能達到100Mbps以上；此高速加密與解密處理器，在未來可以滿足各種不同應用環境對於處理速度上的需求。

關鍵字

子金匙 ； 密碼分析 ； 管線式 ； 可程式化邏輯元件

並列摘要

The aim of this thesis is to design and implement an encryption and decryption chip with IDEA (International Data Encryption Algorithm). It is a block cipher, it encrypts a 64-bit block of plain text into a 64-bit block of cipher text using a 128-bit key. IDEA eight encryption rounds executes continuously with fifty-two 16-bit subkeys which are generated from the 128-bit key. In each round, there will be three arithmetic operations carrying out：“Bit-wise Exclusive-OR”、“Addition modulo 216”、“Multiplication modulo (216+1)”. Although IDEA has been widely introduced since 1992, there is no literature of the cryptanalysis to find weakness being pronounced up to present. In other word, IDEA has resisted all known attempts of cryptanalysis. As we can see, this algorithm definitely has a high security.

Thus, we adopted IDEA as the kernel algorithm in our research for encryption and decryption chip design instead of computing in software. In addition to satisfy various needs under different application environments, we adopt modularize architecture approach for a single chips with the arithmetic operations of two rounds for both encryption and decryption. Such that either system application or processor control interface could be more flexible. We also proposed pipelined parallel processing hardware architecture of the IDEA kernel algorithm, to solve data dependency problem in order to improve performance of the parallel operations. Therefore, the operations speed is enhanced and the system performance could be efficiently reached over 100Mbps of the computing power as we expected. We believe that such high-speed processing capability makes the system meet the versatility computing of cryptograph application.

並列關鍵字

Subkey ； Cryptanalysis ； Pipelined ； Complex Programmable Logic Device

參考文獻

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Signatures and Public-Key Cryptosystems﹐" Communication of the ACM.

Springer Verlag，Berlin，1994.

[8] H. Bonnenberh﹐et al. "VLSI Implementation of a New Block Cipher﹐" in

[9] G. A. Jullien﹐"Implementation of multiplication﹐modulo a prime number﹐