快速串音時序分析的耦合延遲特徵化

Coupling Delay Characterization for Fast Crosstalk Aware Timing Analysis

邱浚智(Chun-Chih Chiu)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2004年)

摘要

半導體製程的進步，特徵尺寸也不斷的縮小。越來越靠近的導線間距，使得位於導線間的耦合電容（coupling capacitance）也隨之增加，並且耦合電容所造成的耦合延遲（coupling delay）已經是影響互連延遲（interconnect delay）的主要因數。有多種參數與耦合延遲有關，如驅動邏輯閘(driving gates)，驅動強度(driving strength)，輸入信號的轉換方向(input signal switching direction)，輸入信號的傾協度(input single slew rate)，以及互連線路的寬度與長度。若不藉助SPICE模擬是很難取得精確的耦合延遲。然而，有效率的計算耦合延遲對於靜態時序分析而言是相當重要的。為了達成這個目標，耦合延遲需要先被特徵化並且形成一個容易取得的資料庫。在這篇論文中，我們使用曲線契合方法(curve fitting method)來取得可以計算耦合延遲的封閉形式方程式（closed-form equation）。這些封閉形式方程式的R-Square 值皆大於 0.99。我們將HSPICE所產生的200組結果來驗證這些封閉形式方程式的準確率。我們將使用封閉形式方程式所產生的結果與HSPICE所取得的結果作比較。在耦合延遲上，最大的相對誤差(maximum relative error)為22.46%, 最大的平均絕對誤差(average of absolute)為6.04E-12秒。而在信號的傾協度上，最大的相對誤差為22.46%, 最大的平均絕對誤差為6.04E-12 秒。這些封閉形式方程式也運用於幾個電路範例，所求得的結果將與HSPICE所得的結果作比較。再沒有受到耦合延遲的電路中，延遲的最大相對誤差為14.76%，信號的傾協度的最大相對誤差為13.05%。再受到單獨侵略者的電路中，延遲的最大相對誤差為101%，信號的傾協度的最大相對誤差為81.83%。再受到多個獨侵略者的電路中，延遲的最大相對誤差為259.4%，信號的傾協度的最大相對誤差為87.03%。這些封閉形式方程式用於靜態時序分析中，當絕對誤差很小時，大的相對誤差是可以被接受的。

關鍵字

特徵化 ； 串音 ； 時序分析 ； 耦合延遲

並列摘要

Advance in process technologies has led to decrease in feature size of the transistors. With reduced wires spacing, coupling capacitance between wires increases significant. The coupling capacitance becomes a critical factor in deciding circuit delay. Since coupling delay depends on many factors such as the use of driving gates, driving strengths, input signal switching direction, input slew rate, and the interconnect length and width. It is difficult to obtain accurate coupling delay without resort to SPICE simulation. However, it is utmost important for a static timing analysis tool to compute coupling delay efficiently. To achieve this goal, the coupling delay should be pre-characterized and formed an easily accessible database. In this thesis, we perform coupling delay characterization. We use the curve fitting method to obtain the closed-form equations for computing coupling delay. The R-Square of these closed-form equations are higher than 0.99. We then verify the accuracy of closed-from equation using the 200 results obtained by HSPICE. We use the closed-from equations to calculate coupling delay and transition time with same circuit parameters as that used by HSPICE. In the coupling delays, the maximum relative error is 22.46% and the maximum average of absolute error is 6.04E-12s. In the transition times, the maximum relative error is 27.90% and the maximum average of absolute errors is 9.11E-12s. We also employ the closed-form equation s to calculate delay on several circuit instances. We compare the results calculated by closed-form equations with the results obtain by HSPICE. In a noiseless circuit, the maximum relative error is 14.76% of delay and the maximum relative error is 13.05% of the transition time. In the circuit with a single aggressor, the maximum relative error for the delay at output is 101% and the maximum relative error of transition time at the output is 81.83%. In the circuit with multi-aggressors, the maximum relative error is 259.4% of delay and the maximum relative error is 87.03% of the transition time. In the circuit with global crosstalk problem, the maximum relative error is 97.59% of delay and the maximum relative error is 80.59% of the transition time. When the closed-from equations are used to calculate the delay in static timing analysis, the high relative error does not matter when the absolute error is extremely small. The higher relative errors in each case described above are acceptable, because the absolute errors are extremely small.

並列關鍵字

Characterization ； Crosstalk ； Timing Analysis ； coupling delay

參考文獻

[CHENP00] Pinhong Chen, Desmond A. Kirkpatrick, and Kurt Keutzer, "Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise," IEEE/ACM International Conference on Computer-Aided Design, pp. 331-337, 2000.

[CHENP02] Pinhong Chen, Yuji Kukimoto, and Kurt Keutzer, "Refining Switching Window by Time Slots for Crosstalk Noise Calculation," IEEE/ACM International Conference on Computer-Aided Design, pp. 583-586, 2002.

[KAH00] A. B. Kahng, S. Muddu, and E. Sarto, "On switch factor based analysis of coupled RC interconnects," Proc. DAC, pp. 79-84, 2000.

[SAS00a] Y. Sasaki and K. Yano, "Multi-Aggressor Relative Window Method for Timing Analysis Including Crosstalk Delay Degradation," Proceedings of the IEEE on Custom Integrated Circuits Conference, pp. 495-498, 2000.

[SAS00b] Y. Sasaki and K. Yano, "Building a Crosstalk Library for Relative Window Methods-Timing Analysis That Includes Crosstalk Delay Degradation," Proceedings of the Second IEEE Asia Pacific Conference on ASICs, pp. 371-374, 2000.