超大型積體電路內部導體連線之電容特徵化

VLSI Interconnect Capacitance Characterization

周文祥(Wen-Hsiang Chou)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2004年)

摘要

在深次微米的電路設計中，導體連線的電氣特性對晶片設計上變得相當重要，並且在訊號完整性的問題上扮演著重要的角色。訊號完整性問題主要可分幾個部份。耦合電容對串音(Crosstalk)的影響，電源導線上的電壓降(IR Drop)，半導體製程上的變異等。串音的問題將造成訊號的延遲或者出現不確定性突波(glitch)，其主要是由兩相鄰導體間之耦合電容所造成。因此耦合電容對於串因音問題上為一重要參數。令一個問題是為了改善製程上所造成的變異，在晶片空餘處加入冗餘的金屬塊(Dummy Metal)。此步驟將會對耦合電容造成重大的影響，因此在我們的實驗中將會去考慮這兩個因素。
論文中我們將會去討論導體連線之幾何結構及導線於晶片上的分佈密度對於耦合電容的影響。在實驗中分為兩個部份：一個結構是僅有導體連線，另一個是有加入冗餘的金屬塊。在實驗結果中我們推導計算兩導體間之耦合電容的公式，並且歸納一些規則可去建立一個快速的全晶片電容萃取程式。

關鍵字

耦合電容 ； 串音 ； 電容特徵化

並列摘要

In the ultra deep sub micron (UDSM) designs, the electrical properties of the conducting wires have become increasingly important so that they play an important role in maintaining signal integrity (SI). SI problem manifests itself in various ways. The crosstalk due to wire coupling, IR drop on supply and grounded bus etc. are main sources of SI problems. Crosstalk can either cause signal delay variation that may lead to timing violations or unintended glitches that may lead to functional failures. Hence, the coupling capacitance is an important parameter for SI.
In this thesis, we will study how capacitance is varying with geometry dimension and topological structure of wires. We experiments with two different structures, the structures including dummy metals and the structures not including dummy metals. We observed that the total and coupling capacitance are not much influenced by the distribution of the dummy metal on top and bottom layers when metal density is larger than 30%. This is also trace for the non-dummy metal structures. Many rules such as this one are derived from our experimental results. They are very suitable for being used in fast full-chip interconnect capacitance extractions.

並列關鍵字

coupling capacitance ； crosstalk ； Capacitance Characterization

參考文獻

[ARO96] N. D. Arora, K. V. Raol, R. Schumann and L. M. Richardson, “Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits”, IEEE Trans. on Computer-Aided Design, vol. 15 no.1 Jan. 1996

[BAK88] Erich Barke, “Line-to-Ground Capacitance Calculation for VLSI: A Comparison”, IEEE Trans. on Computer-Aided Design, vol. 7, no. 2, 1988.

[CON97] Jason Cong, Lei He, A.B. Kahng, David Noice, Nagesh Shirali and Steve H.-C. Yen, “Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology”, Proc. ACM/IEEE Design Automation Conference, June 1997

[CHE02] Y. Chen, A.B. Kahng, G. Robins and A. Zelikovsky, “Closing the Smoothness and Uniformity Gap in Area Fill Synthesis”, Proc. ACM/IEEE ISPD, April 2002

[CHE03] Y. Chen, P. Gupta and A.B. Kahng, “Performance-Impact Limited Area Fill Synthesis”, Proc. ACM/IEEE Design Automation Conf. June 2003