兩級四階具可適性數位補償之16位元類比/數位和差調變器

Tow-Stage Fourth-Order 16-bit Sigma-Delta Analog-to-Digital

黃翊嘉(Yi-Chia Huang)

指導教授 ： 吳紹懋

元智大學/工程學院/電機工程學系/碩士(2000年)

摘要

本論文研究設計一個高解析度兩級四階Cascaded Sigma-Delta具可適性數位補償之超取樣(Oversampling)類比數位調變。
此調變器的設計是以差動交換電容電路（Fully Differential Switched Capacitor）的技術來達成，並利用超取樣率（Oversampling Ratio, OSR）、雜訊移頻（Noise Shaping）、多級順向（Multi-stAge noiSe sHaping, MASH）等等類比調變器設計方法，及可適性數位補償消除漏雜訊（Noise-leakage）的發生，以提升整體的效能。可適性數位補償部份可在數位處理器（DSP）中達成。此調變器的解析度可達16-bit之高，而信號範圍為基頻48KHz 範圍。此一規格的調變器將可應用於AC97 (Intel Audio Codec 97) 介面中。其系統取樣頻率為12.28MHz，超取樣率為128倍，訊號雜訊比為98.73dB，使用3.3V電源，消耗功率為33.3429mW，佈局面積為711.414μm×644.336μm，晶片面積為1091μm×1091μm，使用的製程技術為台灣積體電路製造公司(TSMC) 0.35μm 2P4M製程。

關鍵字

sigma delta ； 多級順向 ； 超取樣 ； 交擙電容 ； 並聯 ； 可適性 ； 數位補償 ； 雜訊移頻

並列摘要

In this thesis, we propose a high-resolution two-stage fourth-order cascaded Sigma-Delta oversampling Analog-to-Digital modulator with adaptive digital compensation.
The modulator is implemented with fully differential switched capacitor circuits, over-sampling ratio, noise shaping, multi-stage noise shaping, and adaptive digital noise-leakage compensation. The modulator achieves a resolution of 16-bit and the signal bandwidth is 48KHz. The specification is fit for Intel Audio Codec 97 interface. The system is driven by 12.28MHz, and the OSR is 128, the SNR is 98.73dB, the power supply is 3.3V, the power consumption is 33.3429mW, the modulator layout area is 711.414μm×644.336μm, and the chip area is 1091μm×1091μm. The fabrication technology is TSMC 0.35μm 2P4M technology.

並列關鍵字

sigma delta ； MASH 2-2 ； oversampling ； Switched Capacitor ； cascaded ； adaptive ； digital compensation ； noise shaping

參考文獻

[AlH87] Phillip E. Allen and Douglas R. Holberg, "CMOS Analog Circuit Design," Oxford, 1987.

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[CaG85] R. Castello and P. R. Gray, "A High-Performance Micropower Switched-Capacitor Filter," IEEE J. of Solid-State Circuits, Vol.20, no. 6, pp.1122-1132, December 1985.

[Fel97] Arnold R. Feldman "High-Speed Low-Power Sigma-Delta Modulator for RF Baseband Channel Applications," PhD Dissertation, University of California, Berkeley, September 1997.

[GMS99] Yves Geerts, Augusto Manuel Marques, Michel S. J. Steyaert, Willy Sansen, "A 3.3-V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications," IEEE J. Solid-State Circuits, Vol. 34, NO.7, July 1999.