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  • 學位論文

耦合雜訊下靜態時序分析相關議題之研究

Issues on Coupling-Aware Static Timing Analysis

指導教授 : 林榮彬
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摘要


無資料

關鍵字

靜態時序分析 串音

並列摘要


Semiconductor process technology has advanced to the point where wire delay is becoming relatively larger than gate delay such that gate delay no longer dominates the longest path delay. Especially, coupling capacitance becomes a dominant factor in deciding wire delay. Crosstalk-induced delay becomes quite significant and difficult to determine because of dependency on neighboring signals. To more accurately compute coupling delay, an iterative process is used to compute the switching window of a signal in a STA. However, the switching windows are converged to different solutions depending on the initial assumptions for an iterative STA. Most of the STAs assume there is only one continuous switching window on the fanout node of a gate even if the gate has multiple inputs. In this situation, they do not accurately consider temporal isolation. They also do not consider the effect caused by a synchronization point, i.e., a signal branching out at the fanout of a gate and being propagated along different paths. In this thesis, we develop a coupling-aware static timing analyzer with considering synchronization points (SPs) and multiple timing windows. We observe that path delay change with considering SPs ranges from —10% to 17% for the underlying test circuit.

並列關鍵字

Static Timing Analysis Crosstalk

參考文獻


[ARUN02] Ravishankar Arunachalam, Ronald Deshawn Blanton, and Lawrence T. Pileggi, "Accurate Coupling-Centric Timing Analysis Incorporating Temporal and Functional Isolation," VLSI Design, pp. 605-618, 2002.
[BRA88] Daniel Brand and Vijay S. Iyengar, "Timing Analysis Using Functional Analysis," IEEE Transactions on Computers, vol. 37, pp.1039-1314, 1988.
[CHENP00] Pinhong Chen, Desmond A. Kirkpatrick, and Kurt Keutzer, "Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise," IEEE/ACM International Conference on Computer-Aided Design, pp. 331-337, 2000.
[CHENP02] Pinhong Chen, Yuji Kuki moto, Chin-chi Teng, Kurt Keutzer, "On Convergence of Switching Windows Computation in Presence of Crosstalk Noise," ISPD, pp. 84-88, 2002.
[DAR97] Florentin Dartu and Lawrence T. Pileggi, "Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling," Proceedings of IEEE/ACM Design Automation Conference, pp. 46-51, 1997.

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