Semiconductor process technology has advanced to the point where wire delay is becoming relatively larger than gate delay such that gate delay no longer dominates the longest path delay. Especially, coupling capacitance becomes a dominant factor in deciding wire delay. Crosstalk-induced delay becomes quite significant and difficult to determine because of dependency on neighboring signals. To more accurately compute coupling delay, an iterative process is used to compute the switching window of a signal in a STA. However, the switching windows are converged to different solutions depending on the initial assumptions for an iterative STA. Most of the STAs assume there is only one continuous switching window on the fanout node of a gate even if the gate has multiple inputs. In this situation, they do not accurately consider temporal isolation. They also do not consider the effect caused by a synchronization point, i.e., a signal branching out at the fanout of a gate and being propagated along different paths. In this thesis, we develop a coupling-aware static timing analyzer with considering synchronization points (SPs) and multiple timing windows. We observe that path delay change with considering SPs ranges from —10% to 17% for the underlying test circuit.