全數位可適應性頻寬鎖相迴路設計分析與實現

Design, Implementation and Analysis of All Digital Adaptive-Bandwidth PLL

蔡坤達(Kun-Da Tsai)

指導教授 ： 趙燿庚

元智大學/工程學院/通訊工程學系/碩士(2006年)

https://doi.org/10.6838/YZU.2006.00008

摘要

鎖相迴路係用於同步系統，例如LCD Driver、Digital TV之Tuner等等。鎖相迴路之設計在可適應性調整頻寬下，可使得更大之頻率範圍、製程、電壓和溫度的變動下達到最佳效能。在傳統之可適應性鎖相迴路架構中，充電泵必須利用電阻與電容，較難控制類比參數 與 去調整充電泵達成Adaptive-Bandwidth PLL，且無法構成單晶片形式，增加製作成本負擔。
因此我們設計了一個新架構之Adaptive-Bandwidth ADPLL，改善傳統式鎖相迴路缺點，並採用UMC 0.18um 1P6M CMOS製程以ASIC Design Flow設計與實現之。

關鍵字

可適應性頻寬；鎖相迴路；全數位鎖相迴路

並列摘要

Phase Locked Loop (PLL) is used in synchronous communication system. For example, it can be used to the LCD Driver, Tuner of the Digital TV, etc. A PLL design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and temperature variations. In the traditional Adaptive-Bandwidth PLL scheme, the charge pump must consist of resistors and capacitors. However, it is challenging to control the analog parameter and to adjust the charge pump to achieve the Adaptive-Bandwidth PLL. Moreover, the Adaptive-Bandwidth PLL can’t be the component of SOC form, so it increases the cost.
Hence, we proposed a novel architecture of Adaptive-Bandwidth ADPLL to solve the problems in traditional Adaptive-Bandwidth PLL. We used the ASIC (Application Specific Integrated Circuit) Design Flow to design and implement Adaptive-Bandwidth ADPLL by UMC 0.18um 1P6M CMOS process.

並列關鍵字

Adaptive-Bandwidth；PLL；ADPLL

參考文獻

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