本篇論文中,提出了一個合併測試資料的方法,來減少測試時所需的測試資料量和測試時間,因為test set中存在許多don’t care bits (X-bits),在測試時,這些bits的值不論給0或1,皆不會影響測試結果,因此可以將這些bits加以利用來達到資料的合併效果。所提出的方法是利用test set中某些column間彼此的compatibility特性,加以合併以減少原本的test set中的column個數,亦減少每個test pattern的bits總數。並依合併結果,重新建構scan chain,將原本的single scan chain切割成multiple scan chain,並利用scan chain disable signal (SCDS)來控制每段scan chain的shift clock,因此,multiple scan chain可以共享合併後的shared test set。跟傳統的壓縮方法不同的地方,所提出方法不需要額外的decoder來還原測試資料,因此可以利用較少的硬體成本,來達到壓縮和解壓縮的效果。另外,提出的方法不但可以減少測試資料(約60.39%),尤其在節省測試時間(約59.75%)上有很大的效益。
This thesis proposes a method to reducing the test data volume and the test application time by compressing the test data during test. Usually, there are many don’t-care bits (X-bits) in a test set and these X-bits can be are assigned as 1 or 0 without affecting the test result, these X-bits can be used for the test data compression. The proposed method uses the compatibility among the columns to reduce the number of columns in a test set. In other words, it will reduce the number of bits in each test pattern. Then, a single scan chain is re-constructed into multiple scan chains according to the compression result. The test data for multiple scan chains can be applied simultaneously by using scan chain disable signal (SCDS) to control the shift clock of each scan chain. Being different from the conventional compression methods, the proposed method decompresses the test data without any decoder. Therefore, the hardware cost for this compression/decompression approach is low. Experimental results for some ISCAS’89 benchmark circuits show that the proposed method reduces not only the test data volume (about 60.39%) but also the test application time (about 59.75%).