透過您的圖書館登入
IP:3.133.109.30
  • 學位論文

低功率消耗之測試資料產生方法

Low Power Test Pattern Generation

指導教授 : 曾王道

摘要


這篇論文提出了一個可同時降低shift power和capture power的test patterns產生方法。最主要是利用D-algorithm和SCOAP方法來實作。我們在SCOAP演算法中調整state inputs和primary inputs的controllability初始值,以及調整state outputs和primary outputs的observability初始值,盡可能將fault effect儘量引導到primary outputs,以減少capture動作的產生;同時也希望test pattern中的care bits能夠集中在primary inputs。然後,當我們用D-algorithm產生測試資料時,經由justify去找出相對應的test pattern。另外,我們也將scan chain切割成n個segments,讓僅有部分的scan chain被啟動,借此來降低shift power。從實驗結果來看,我們的做法確實能夠減少capture power和shift power。

並列摘要


This paper presents a method to produce test patterns which can reduce shift power and capture power. The method is implemented by D-algorithm and SCOAP. By setting the initial controllability values of state inputs and primary inputs, and setting the initial observability values of state outputs and primary outputs, and propagating the faults to primary outputs as far as possible, so the numbesr of capture will be reduced .And we loacate care bits possible on primary inputs, then we find the corrsponding pattern by justify when producing the test data using D-algorithm. By the way, we partition the scan chain into n segments, and we enable partial od scan chain to reduce shift power. By the experimental results, the method reduces the capture power efficiently by reducing the numbers of the capture action, and the shift power is reduced by partitioning the scan chain.

參考文獻


[2] Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang,
Kewal K. Saluja, and Kozo Kinoshita, “On Low-Capture-Power Test Generation for
1-5 May 2005 Page(s):265 – 270.
[3] K. Miyase and S. Kajihara, “XID: Don't Care Identification of Test Patterns for
Combinational Circuits,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 2, pp.

延伸閱讀