- 學位論文
減少擷取時間能量消耗之測試資料產生方法
Test Pattern Generation for Capture Power Reduction
摘要
由於實體電路的設計越來越複雜，超大型積體電路測試時的功率消耗成為一個重要的議題。對於以掃瞄為基礎的測試架構中(scan based testing architecture)，過多的0-1轉換活動(switching activities)所造成的功率消耗佔整體測試功率消耗的大部分。而在擷取測試結果(test response)時，大量的功率消耗會引起過多的電源電壓下降(IR drop)，影響測試結果並造成顯著的良率損失。因此本篇論文提出一個測試資料產生方法以減少在擷取測試結果時所造成的能量消耗。指定隨意位元(don’t care bit)的值為0或1並不會對錯誤偵測率(fault coverage)造成影響。因此我們主要的概念是透過D-algorithm產生測試資料。在D-演算法(D-algorithm)中決定錯誤傳遞路徑與原路返回路徑來產生測試資料需考慮SCOAP分析的結果；為了減少在擷取測試結果時的0-1轉換，產生測試向量(test vector)時把隨意位元集中在欲送進掃瞄鏈(scan chain)的部分。而我們提出的方法可以減少在擷取測試結果時的功率損耗而不需要額外的硬體來完成，也不影響電路效能。
關鍵字
能量並列摘要
Power dissipation has become an important issue in VLSI testing due to the growing complexity of designing integrated circuits. In scan-based testing, switching activity dominates total power consumption. Additionally, high power dissipation causes excessive IR drop during capture cycles and thus the loss of yield is significant. In this thesis we proposed a test pattern generation method to reduce the power dissipation during capture cycle. As the fault coverage will not be affected by assigning the don’t care bits, the proposed method is based on generating a test set by D-algorithm. For reducing transitions of the capture cycle, don’t care bits of the test vector generated by D-algorithm can be concentrated on the portion of test vector shifted into scan chain according to SCAOP analysis. The proposed method reduces switching activity in capture mode without increasing any area overhead and decreasing the performance of circuits.