Due to Dynamic Partial Reconfiguration, currently configuration algorithms often spend a lot of time looking for the available FPGA space, and affecting the overall system performance. In this paper used an algorithm to search configuration and the remaining space that hardware resources management. Implementation of the Xilinx ISE 9.2i and the Verilog hardware description language implementation to simulate that remaining space, and according to different tap of the FIR (Finite Impulse Response, FIR) filter, the use Dynamic Partial Reconfiguration to change the tap of the number then Search the maximum available rectangle. Function is implemented on Xilinx Virtex-5 FPGA development board for verification. Program is written using Visual C # 2008 for a resource management system of the Windows program.