快速頻率合成器與可適性全數位鎖相迴路之設計與實現

The Design of High Speed Digital Frequency Synthesizer and All-Digital Phase-Locked Loop with an Adaptive Bandwidth

陳振豐(Chen-Feng Chen)

指導教授 ： 趙燿庚

元智大學/電機通訊學院/電機工程學系/博士(2011年)

https://doi.org/10.6838/YZU.2011.00073

摘要

本論文分成快速頻率合成器與可適性全數位鎖相迴路之設計與實現兩大部分來探討。首先，就高速數位頻率合成器而言，基於模組-N電路的特性，架構出ㄧ個新的高性能頻率合成器。在此電路中，使用一組方波，具相同頻率但不同相位的訊號，透過葛雷編碼多工器，用意在於消除脈衝波的干擾問題。基於前述架構，我們再使用兩個控制字元去產生可控制之責任週期，且分析所合成頻率與責任週期的解析度。另外，第二部份的電路為將ㄧ個二階連續時間訊號模型透過z轉換成二階離散時間之模型，藉此推導出二階可適性全數位鎖相迴路之設計準則與流程，並利用所推導之準則，該二階可適性全數位鎖相迴路即可調整其系統參數去平衡迴路雜訊頻寬與鎖相的時間。按此準則來設計，即可使迴路頻寬與參考輸入訊號頻率比為常數。

關鍵字

Frequency synthesizer ； Adaptive-Bandwidth All-Digital phase locked loop ； Gray-encoded M-to-1 multiplexer ； Jitter

並列摘要

The design of high speed digital frequency synthesizer and all-digital phase-locked loop with an adaptive bandwidth are proposed in this thesis. First, for high speed digital frequency synthesizer, based on the modulo-N arithmetic, a new architecture of high-performance digital frequency synthesizers is devised. A set of square waves with the same frequency but different phases is passed through a Gray-encoded multiplexer, which can be used to eliminate the glitch and to generate pulses with a highest frequency. Moreover, based on the above architecture, the digital frequency synthesiser with a controllable duty-cycle is designed and implemented. For the duty-cycle control, two control words (COWs) are used. To generate the desired frequency and/or duty-cycle with the COWs, another modulo-N incrementer is designed. The resolutions of the synthesised frequencies and duty-cycles are analyzed, and relevant properties of output waves are derived. In addition, in this thesis, an all-digital phase-locked loop with an adaptive bandwidth is proposed, where the second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. For the implementation of the ADB-PLL, a counter-based phase-frequency detector (PFD) is proposed and a time-to-digital converter (TDC) is used to transform the PFD output to a digital signal. In the ADB-ADPLL system, a digital loop filter (DLF) and a digital-controlled oscillator (DCO) are implemented with a modulo-N algorithm and proportional and integral (PI) control. Simulation results are presented to illustrate the performance of the ADB-ADPLL.

並列關鍵字

頻率合成器 ； 可適性頻寬全數位鎖相迴路 ； 葛雷編碼 M 對1多工器 ； 抖動線現象

參考文獻

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