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  • 學位論文

3~5GHz 利用回授與current reuse/current bleeding技術之 微型化接收機

3~5GHz current reuse/current bleeding compact receiver front-end with feedback technique

指導教授 : 楊正任

摘要


本論文為因應UWB系統特色-低系統複雜度、低製造成本、低消耗功率,研究使用較少晶片面積,以達到降低成本的需求的方式來完成應用於UWB系統的接收機前端電路設計,所有設計皆採用TSMC 0.18?m COMS 製程。其中包含三個實際製作完成之電路,皆以減少電感元件使用量為目標,分別為一3~5GHz 單電感匹配低雜訊放大器,其增益為15.7±0.25dB,雜訊指數小於3dB,晶片面積0.6mm²,並應用此低雜訊放大器設計一3~5GHz 接收機,其增益為18±1dB,雜訊指數小於3.5dB,晶片面積0.93mm²;另外設計一3~8GHz 單電感寬頻混頻器,其增益為15.2±0.5dB,雜訊指數小於10.5dB,晶片面積0.5mm²;且以上晶片量測結果皆達到預期目標。 最後設計一使用變壓器隔離方法研製0.6V低偏壓WiMAX接收機,電路設計皆採用低偏壓的方式來降低電率功率消耗,整體電路皆在0.6V即可驅動,在0.6V/10.6mW的消耗下,整體電路增益達到23.5dB,雜訊指數為3.87dB。

關鍵字

接收機 超寬頻 微型化

並列摘要


To fit the needs of the UWB systems,- low system complexity, low cost, and low power consumption, this study examines methods of reducing the chip area to reduce -costs and develop a receiver front-end circuit design for UWB systems. The design comprises three manufactured circuits. With the 3~ 5GHz low noise amplifier with a single inductor matching network, the gain is 15.7 ± 0.25dB, the noise figure is less than 3dB, and the chip size is 0.6mm ². Using this LNA to design a 3 ~ 5GHz receiver, the gain is 18 ± 1dB, the noise figure is less than 3.5dB, and the chip size is 0.93mm ². Finally, for the design of a 3 ~ 8GHz single inductor mixer device, the gain is15.2 ± 0.5dB, the noise figure is less than 10.5dB, and the chip size is 0.5mm ². The goal of all circuits is to reduce the number of inductors required. All designs use the TSMC 0.18 um CMOS process and all measurement results satisfied the expectations. Additionally, this paper introduces a design of a 3.5GHz transformer based low voltage supply receiver for the WiMAX system. To reduce the power consumption of the system, this study proposes the use of a low voltage structure; the overall circuit can be driven at 0.6V. Using a 0.6V/10.6 mW power supply, a gain of 23.5 dB was be achieved, with a noise figure of 3.87 dB.

並列關鍵字

receiver UWB compact

參考文獻


[6] 潘士安,「應用於9-band OFDM 超寬頻系統低電壓接收機之前端射頻積體電路設計」元智大學通訊工程學系,碩士論文,2008。
[3] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill.
[4] Aly Ismail and Asad A. Abidi, “A 3–10-GHz Low-Noise Amplifier With Wideband LC-Ladder Matching Network,” IEEE Journal of Solid-State Circuits, Vol. 39, pp.2269-2277, Dec. 2004.
[7] Choong-Yul Cha and Sang-Gug Lee, "A 5.2-GHz LNA in 0.35-µm CMOS Utilizing Inter-Stage Series Resonance and Optimizing the Substrate Resistance," IEEE J. Solid-State Circuits, vol. 38, pp. 669–672, Apr. 2003.
[8] Taris, T.et al, “A low voltage current reuse LNA in a 130nm CMOS technology for UWB applications,” Microwave integrated circuit conference, pp.307-310,Oct. 2007.

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