HDI印刷電路板填孔龜裂檢出最佳化之研究- 運用實驗設計法

The Optimum Method to Detect HDI PCB Fill Via Crack Problem - Design of Experiment

賴志明(Chih-Ming Lai)

指導教授 ： 陳雲岫

元智大學/工程學院/工業工程與管理學系/碩士(2012年)

https://doi.org/10.6838/YZU.2012.00079

摘要

本論文在探討電子產品輕薄短小且功能性越多的趨勢下，印刷電路板也趨朝向更高階ELIC(Every Layer Interconnection)逐層互連技術，所以每一顆盲孔都扮演導通角色其連結的完整性就十分重要，因此如何利用品質驗證的手法有效減出異常，是本論文探討的議題。
利用DOE(Design of Experiment)實驗設計的手法，先找出Thermal shock、Thermal stress、Reflow等3項因子，以2^3全因子進行實驗，找出顯著的因子，再以Thermal stress單因子3水準，找出影響阻值變化R shift最顯著的條件：260度/20秒/5 cycle，經再現性確認該條件確實有效將盲孔crack異常有效檢出，避免PCB經組裝後，電子產品功能性異常，造成嚴重的客戶抱怨及巨額的賠款。

關鍵字

印刷電路板 ； 高密度互連 ； 逐層互連 ； 實驗設計

並列摘要

The consumer product trend achieve thin and small, but more func-tion requirement. PCB manufactures have to use ELIC(Every Layer In-terconnection) technology to satisfy customer needs. That means each via connected reliability in ELIC structure is all important. Then how to find out a optimum method to detect crack high risk issue is a big topic that we discuss.
First we choice thermal shock, thermal stress, reflow,three factors. To perform 23 factorial experiments to find out significant factor –Ther-mal stress. To perform one factor and 3 levels experiment to decide an optimum method and detect high risk via. This optimum condition: 260℃/ 20 second/ 5 cycle could effectively to detect filled via crack .This result can prevent the crack big issue to reveal to customer side and cause serious complain and reparation.

並列關鍵字

PCB(Printed Circuit Board) ； HDI(High Density Interconnection) ； ELIC(Every Layer Interconnection) ； DOE(Design of Experiment)

參考文獻

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