摘要
在超大型積體電路測試中，越來越龐大的測試資料導致測試時間以及測試成本的提高是目前所面臨的議題。在本篇論文中我們提出一種可以有效減少工業用測試資料的方法，來面對日與劇增的測試資料。有別於以往多掃描鏈架構下測試資料的壓縮方式，我們提出來的方法不是單純的只針對每筆切片做處理，更是結合了運行長度編碼的技巧來進一步的讓測試資料得到更好的壓縮率。在本篇論文中所提出的方法不需要動到任何待測電路內部架構，也不需要特定的演算法，我們只利用一些測試資料特徵，像是利用切片與切片之間測試資料重複的特徵、切片內資料重複的特徵或者在每個切片中的特殊比特的索引值來決定我們要用哪一種編碼方式。編碼也不同於一般的編碼方式，編碼的長度是不固定的，而是根據不同的資料特徵來決定適合的編碼長度。我們的硬體架構很簡單，只需要簡單的緩衝器、解碼器及數個計數器即可。實驗結果中採用ISACS89的測試電路來做為實驗電路，最後從實驗結果中可以發現，隨著電路的增大，如我們一開始預期般的一樣，其效率會越明顯，這是在多掃描鏈的架構下可以展現出來它的效能。
關鍵字
測試資料壓縮並列摘要
In traditional testing research for testing VLSI circuits, the larger and larger amounts of test data volume increasing the test time and test cost very much. In this thesis, we proposed an effective compression method to reduce large amounts of test data volume for multiple-scan testing. Different from other compression methods using multiple scan chains, in this method, we not only deal with each slice but also combine the run-length-based technique. There is no need to change the internal structure of CUT, nor do we use a particular algorithm. We use the some traits in each slice like the repeated data between each slice or the repeated data in each slice or specific bits in each slice. Our codeword is quite different. The length of each codeword is not fixed. We will decide the length of each codeword by different traits in each slice. Our hardware structure is simple, only a buffer, a decoder and several counters are needed. We use ISCAS-89 benchmark circuits in our experiment. We can see the experiment results show that our method is especially effective as the circuit size grows.