以0.18μm CMOS製程研製LTE微型化接收機及陣列組合高功率發射機

本論文之LTE收發機前端電路是利用TSMC 0.18μm 1P6M CMOS製程研製其中包含三個實際下線之電路為0.7~2.6GHz高線性度低雜訊放大器與0.7~2.7GHz高線性度降頻混頻器與1.7GHz具變壓巴倫器之高輸出功率發射機前端電路與3~10GHz超寬頻低雜訊放大器。0.7~2.6GHz 高線性度低雜訊放大器是採用雜訊抵銷與失真抵銷架構來完成高線性度與低雜訊的特性，模擬結果增益為10.2~12.2dB、雜訊為2.3~3.1dB、S11、S22皆小於-10dB，IIP3在1.7GHz達到+8dBm，並採用TSMC 0.18μm製程實際下線。0.7~2.6GHz 高線性度降頻混頻器，採用多閘極技術架構，有效提高線性度並避免功耗過大與偏壓過高的問題，偏壓僅維持在1.2V，並無使用電感節省不少面積，模擬結果轉換增益在5.8~7.2dB，功耗9.6mw、IIP3在2.3GHz時達+13.5dBm，並採用TSMC 0.18μm製程實際下線。1.7GHz具變壓巴倫器之高輸出功率發射機前端電路設計採用混頻器陣列排列方式，使混頻器單元在排成陣列後具有高功率輸出以做功率放大器，完成整個發射機前端電路的設計，此方式節省不少面積，並完成0.5W輸出功率之全積體化發射機前端電路設計，將電流匯流到變壓巴倫器轉為單端輸出的方式亦解決了已往以CMOS製程實現全積體化高功率輸出電晶體崩潰電壓太低的問題，模擬結果增益為24dB，P1dB為+3dBm，P1dB點的輸出功率為+27dBm，效率為19%，供應電壓為3V。3~10GHz超寬頻低雜訊放大器設計輸入匹配採用高通濾波電路，僅用一個電感以節省面積，中間放大級採用電流再利用架構節省電流消耗並進一步增加增益，輸出匹配採用源極追隨器完成3~10GHz寬頻匹配，量測結果S11與S22皆小於-10dB，增益10~13dB，功耗10.32mw，雜訊最小為3.9dB，偏壓1.2V。

關鍵字

LTE ；接收機；發射機

並列摘要

This paper uses a TSMC 0.18μm CMOS process to design RX/TX front end for LTE systems. Three manufactures were commissioned to create the electric circuits 0.7~2.6GHz LNA, 0.7~2.7GHz mixer, 1.7GHz tranmitter front end with transformer balun and 3~10GHz UWB LNA. The 0.7~2.6GHz LNA uses noise- and distortion- cancellation technique to achieve high linearity and low noise figure. Simulation result demonstrates the following performances of the design: the gain is 10.2~12.2dB, noise figure is 2.3~3.1dB, both S11 and S22 are lower than -10dB, IIP3 is +8dBm at 1.7GHz, and this design is implemented by TSMC 0.18μm process. The 0.7~2.6GHz mixer uses multi-gate technique to achieve high linearity and low voltage supply, 1.2V. This design has low die area without using inductor. Simulation result demonstrates the following performances of the design: the conversion gain is 5.8~7.2dB, Pdc is 9.6 mw, IIP3 is +13dBm at 2.3GHz, and this design is implemented by TSMC 0.18μm process. 1.7GHz high output power TX front end with transformer balun uses mixer array to achieve a fully integrated high output power TX front end circuit design. This design has low die area with 0.5W output power by using transformer balun to combine the current output. So it does not have the low breakdown voltage problem. Simulation result demonstrates the following performances of the design: gain is 24dB, P1dBis +3dBm, output power is +27dBm at 1-dB compression point, PAE is 19% and voltage supply is 3V. 3~10GHz UWB LNA is uses high pass filter to achieve input matching network with only one inductor. The inter-stage uses current-reused to achieve high gain and low power consumption. The output matching network uses source follower to achieve 3~10GHz wideband matching. The measurement results demonstrate the following performances of the design: both S11 and S22 are lower than -10dB, gain is 10~13dB, power consumption is 10.32mw, minimum noise figure is 3.9dB and voltage supply is 1.2V.

並列關鍵字

LTE ； Receiver ； Transmitter

參考文獻

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以0.18μm CMOS製程研製LTE微型化接收機及陣列組合高功率發射機

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