基於八階多項式近似的ROM-less DDFS之FPGA實現

FPGA Implementation of ROM-less DDFS Based on an 8-order Polynomial Approximation

柯景耀(Ching-Yao Ke)

指導教授 ： 趙燿庚

元智大學/電機通訊學院/通訊工程學系/碩士(2012年)

https://doi.org/10.6838/YZU.2012.00291

摘要

本文根據新式八階多項式近似的餘弦函數實現了無記憶體式直接式數位頻率合成器(ROM-less DDFS)，並用數位平方器來對多項式作簡化實現。利用MATLAB對DDFS系統效能作模擬，無雜波干擾動態範圍(SFDR)作為效能的依據，對於一個良好的DDFS，SFDR數值越高，頻譜的純度也就越佳。

為了驗證DDFS的效能，使用Altera FPGA平台作驗證，並在Quartus II 和ModelSim軟體對編寫的Verilog程式碼進行模擬驗證，得到的模擬結果也與實現結果一致。

關鍵字

直接數位頻率合成器 ； 無記憶體 ； 現場可程式邏輯閘陣列 ； 多項式近似 ； 平方器

並列摘要

A ROM-less direct digital frequency synthesizer (DDFS) is implemented based on a new 8th-order polynomial approximation of a cosine function, where digital square circuits are used to realize the components of the polynomial. MATLAB tools are used to simulate the performance of the DDFS system, where the spurious free dynamic range (SFDR) is employed as the performance factor. For a DDFS with a superior quality, the higher the SFDR, the better the spectrum purity. To validate the performance of the DDFS, the Altera FPGA platform is used with Quartus II and ModelSim, where simulation results based on Verilog implementation are illustrated.

並列關鍵字

square circuit ； DDFS ； ROM-less ； FPGA ； polynomial approximation

參考文獻

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