藉由雙重線性回饋移位暫存器實現低功率內嵌式自我測試

Dual Linear Feedback Shift Register for Low Power BIST

楊雯婷(Wen-Ting Yang)

指導教授 ： 曾王道

元智大學/資訊學院/資訊工程學系/碩士(2012年)

https://doi.org/10.6838/YZU.2012.00339

摘要

在超大型積體電路測試流程中，功率消耗和測試資料量多寡是重要的議題，內建式自我測試是一種可測試設計技術，是利用嵌入測試邏輯閘來偵測電路中的錯誤，線性回饋暫存器則是最常用在低成本內建式自我測試中用於產生測試資料的技術。Dual LFSR reseeding是利用兩個線性回饋暫存器來做reseeding，最後將兩個線性回饋暫存器的輸出做AND或是OR運算，以減少0、1切換個數。本論文研究中，利用兩個線性回饋暫存器，在低功率消耗的情況下，壓縮線性回饋暫存器的長度。做法是一個線性回饋暫存器只產生測試資料中1的部分，另一個線性回饋暫存器則產生1和所需要的0，如此一來，比起需要兩倍資料量來做AND或OR的技術，此方法除了可降低功率消耗之外，也減少了測試資料量。我們將此方法運用在ISCAS’89的電路中，明顯達到了不錯的壓縮結果。

關鍵字

內建式自我測試 ； 線性回饋暫存器 ； 低功率消耗測試 ； 測試資料壓縮

並列摘要

Power consumption and test data volume are two important issues in VLSI testing. BIST (Built-In Self-Test) is a kind of DFT technique, which uses embedded logic gates to detect some faults in circuits. LFSR is commonly used in low overhead BIST to generate test data. Dual LFSR reseeding use two LFSRs to reseed, and the outputs of the different LFSR operate with AND or OR operation, therefore, it can reduce the number of transitions. An improved dual LFSR reseeding technique is pro-posed in this paper, we use two LFSRs, one deal with the test data 1, and the other care about the test data 1 and 0. So, this method can not only reduce the test power but also decrease the test data volume. The average test LFSR length compression is 51.2% in the circuit ISCAS'89.

並列關鍵字

BIST ； LFSR ； low power testing ； test data compression

參考文獻

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