混合運行長度和模組運行長度之資料壓縮法

Hybrid Run-Length and Pattern Run-Length for Test Data Compression

林冠宇(Guan-YuLin 林冠宇)

指導教授 ： 曾王道

元智大學/資訊學院/資訊工程學系/碩士(2012年)

https://doi.org/10.6838/YZU.2012.00340

摘要

為了要節省測試資料量與測試時間，運行長度編碼( run-length coding )是一種常見且有效率的壓縮方法，本論文是以交錯運行長度編碼(Alternating Run-Length Codes)為架構並混合測試樣式運行長度 (Pattern Run- Length)，主要是利用一個區別碼”0000”，來當作Pattern Run-Length 的開端，讓重覆連續測試樣式可以壓縮成更短的資料，進而達到資料壓縮率的提升。最後的實驗結果是以ISCAS’89學術電路測試資料進行測試，而實驗結果證實，本篇論文提出的方法可以提升壓縮率。

關鍵字

運行長度 ； 模組運行 ； 測試資料壓縮

並列摘要

In order to reduce the test data volume and test time, run length coding is an effi-cient and Common compression method. This paper is based on Alternating Run- Length Codes as the framework and hybrid Pattern Run-Length, the main idea is to use the difference code “0000” as the beginning of Pattern Run-Length. To make the repeated and continuous Pattern can be compressed into a shorter data, Repeated continuous Pattern can be compressed into a shorter data, thus achieving the data compression rate enhancement. Experimental results for the large ISCAS’89 benchmark circuits have demonstrated the proposed approach can improve the test data compression ratio.

並列關鍵字

Run-Length ； Pattern Run-Length ； Test Data Compression

參考文獻

[12] Usha S.Mehta, Kankar S. Dasgupta, NiranjanM. Devashrayee,“ Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey,” 2010 VLSI Design, Jan.2010.

[1] A. Chandra and K. Chakrabarty, “Frequency-directed runlength (FDR) codes with application to system-on-a-chip test data compression,” in Proceedings of the 19th IEEE VLSI Test Symposium (VTS ’01), pp. 42–47, Marina Del Rey, Calif, USA, March 2001.

[2] A. Chandra and K. Chakrabarty, “Test data compression and test resource parti-tioning for system-on-a-chip using frequency-directed run-length (FDR) codes,” IEEE Transactions on Computers, vol. 52, no. 8, pp. 1076–1088, 2003.

[3] A. El-Maleh and R. Al-Abaji, “Extended frequency-directed run-length code with improved application to system-on-achip test data compression,” in Proceedings of the 8th IEEE International Conference on Electronic Circuits and Systems (ICECS ’02), vol. 2, pp. 449–452, Dubrovnik, Croatia, September 2002.

[4] A. Chandra and K. Chakrabarty, “Reduction of SOC test data volume, scan power and testing time using alternating runlength codes,” in Proceedings of the 39th Design Automation Conference (DAC ’02), pp. 673–678, New Orleans, La, USA, June 2002.