本論文提出一個被動式RFID標籤的前端電路之設計,此系統是支援ISO15693通訊協定並操作在13.56 MHz的頻率下。在此提出的類比前端電路裡的子電路包括電源收集器、穩壓器、振幅鍵控(ASK)解調器、負載調變器、解碼器和磁場耦合線圈。電路工作所需的能量來自於耦合磁場,電源收集器與穩壓器能在最低10 dBm 情況下提供晶片1.5V 電壓及100uA電流。解調器方面的設計係按照編碼的規則, 1 out of 256 是使用在長距離,1 out of 4 是使用在短距離或高速模式,可支援10%和100%的ASK。負載調變器是改變標籤端負載阻抗使資料回傳,實驗與量測的結果顯示出資料傳輸速率從6.62 kbps 到26.48 kbps。磁場耦合線圈之量測方面,我們在不同的距離下去量測接收到的電壓,以此推導耦合因數k的關係。系統中的解碼器我們使用VHDL去實現,並且使用FPGA做驗證。此晶片採用0.18 μm TSMC MM/RF CMOS 製程,晶片不包含pad的面積為0.859 #westeur024# 0.493 mm2。總功率消耗為11.3 μW, 操作的範圍大約可以到4 cm。
This thesis presents a passive RFID tag front-end design which complies with the ISO15693 protocol in 13.56 MHz frequency. The proposed analog front-end subsystem consists of a power harvester, a voltage regulator, an amplitude shift key (ASK) demodulator, a load modulator, a decoder, and the magnetic field coupling coils. The power for the circuit is harvested from the coupled magnetic field. Under the circumstance of the lowest power of 10 dBm, the power harvester and the voltage regulator can provide a voltage of 1.5V and a current of 100uA. The demodulator complies with the coding rules, 1 out of 256 for long distance and 1out of 4 for short distance or fast mode; it supports both 10% and 100% ASK. The load modulator changes the load impedance to return data; the experimental results show that the data rate ranges from 6.62 to 26.48kb/s. The magnetic-field coupling of the coils are studied, the relationship between the induced voltage and coupling coefficient k are concluded. The chip is designed and fabricated in the 0.18um TSMC MM/RF CMOS process; the core area without pads is 0.859 #westeur024# 0.493 mm2. The decoder is implemented with VHDL and tested in FPGA. The power consumption is about 11.3uW, and the operating range is about 4 cm.