透過您的圖書館登入
IP:18.217.6.114
  • 學位論文

利用CMOS製程設計製作電磁能隙結構傳輸線與其寬頻特性量測

Design and Fabrication of CMOS EBG Transmission Lines With wide-band Characterization measurement

指導教授 : 黃正光
共同指導教授 : 黃建彰

摘要


本篇論文利用半導體製程,以微帶線與傳輸線理論作為基本架構,製作LST (Line-Series-Shunt)校正件,於晶圓級量測機台進行校正驗證,並進行相關的分析與研究;LST校正法,即利用兩段式的校正技術,將自行設計製作LST校正件,利用逆運算方式進行去嵌化動作,獲取待測物的實際散射參數。製作完LST校正件後,經由SEM可發現,製作第一層TEOS oxide隔離層時,原先設計隔離層厚度5500Å,實際製作完成後的厚度僅有4780Å,發現有明顯的減少13%的厚度。而在製作第二層TEOS oxide隔離層時,原設計8000Å厚度,在實際製作出的厚度為7310Å,明顯地也減少了10%的厚度。然而在金屬的厚度掌握度上則較佳;第一層金屬層設計厚度2000Å,實際製作出來厚度為2020Å,誤差比例僅為1%;而在第二層金屬層所設計之厚度5000Å,實際製作出之厚度為5060Å,誤差範圍為1%左右。本此實驗中發現,兩層的金屬層厚度在製作的控制上較佳,但寬度上的比率控制誤差較大;並且在隔離層的Oxide厚度沉積亦有較差的厚度控制。除此之外,第二層金屬層因TEOS未進行CMP(Chemical mechanical polish)步驟緣故,所以製作出的第二層金屬相當不平整,因而影響了後續的高頻量測電性。

並列摘要


This paper use the semiconductor manufacturing process in order to microstrip lines and transmission line theory as the basic framework for the production of LST (Line-Series-Shunt) correction pieces in wafer-level measurements corrected machine authentication, and related analysis and research ; LST calibration method, namely the use of two-stage correction technology to design their own pieces of the production of LST-tuning the use of inverse operation to embedded manner of movement, access to test the actual scattering parameters of objects. Finished pieces of LST after correction, can be found by the SEM, the production of the first TEOS oxide layer isolation layer, the thickness of the original design isolation 5500Å, the actual production only after the completion of the thickness of 4780Å, found to have significantly reduced the thickness of 13%. In the production of the second TEOS oxide layer isolation layer, the thickness of the original design 8000Å, in the actual production of the thickness of 7310Å, obviously to reduce the thickness by 10%. However, the thickness of metal is a better master degree; the design of the first layer of metal layer thickness of 2000Å, the actual production by the thickness of 2020Å, the error ratio of only 1%; and in the second layer of metal layer thickness designed 5000Å, the actual produced thickness of 5060Å, the error range of 1%. Of the this experiment found that two layers of metal layer thickness control in the production of better, but the ratio of the width of the control errors; and the thickness of isolation layer deposition Oxide thickness control is also poor. In addition, the second level metal layers due to TEOS without CMP (Chemical mechanical polish) steps because, so to produce the second layer of metal rather formation, thereby affecting the follow-up of high-frequency electrical measurements.

參考文獻


[1] V. Radisic, Y. Qian, R. Coccioli, and T. Itoh, “Novel 2-D Photonic Bandgap Structure for Microstrip Lines,” IEEE Microwave Guided Wave Lett., vol. 8, no. 2, pp. 69-71, Feb. 1998.
[2] F. R. Yang, Y. Qian, R. Coccioli, and T. Itoh “A Novel Low-Loss Slow-Wave Microstrip Structure,” IEEE Microwave Guided Wave Lett., vol. 8, no. 11, pp. 372-374, Nov. 1998.
[3] F. R. Yang, K. P. Ma, Y. Qian, and T. Itoh, “A Uniplanar Compact Photonic-Bandgap (UC-PBG) Structure and Its Applications for Microwave Circuits,” IEEE Trans., Microwave Theory Tech., vol. 47, no. 8, pp. 1509-1514, Aug. 1999.
[5] 林保君,〈ㄧ種改良式電磁能隙結構及其應用〉元智大學碩士論文,2007。
[6] T. L. Wu, Y. H. Lin, T. K. Wang, C. C. Wang, and S. T. Chen, “Electromagnetic Bandgap Power/Ground Planes for Wideband Suppression of Ground Bounce Noise and Radiated Emission in High-Speed Circuits,” IEEE Trans., Microwave Theory Tech., vol. 53, no. 9, pp. 2935-2942, Sep. 2005.

延伸閱讀