針對結構化客製晶片設計一類似標準元件之穿孔可程式化的查表基本單元

Standard Cell Like Via-Configurable Look-Up-Table Design for Structured ASICs

逄皓宇(Hou-Yu Pang)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2008年)

https://doi.org/10.6838/YZU.2008.00302

摘要

目前受歡迎的IC 設計方法，ASIC和FPGA，正面臨一項大的挑戰︰ 取得在光罩費用和性能之間的適當平衡。可結構化客製晶片保留ASIC設計的一些特性，例如高效能和使用更小的面積以及擁有FPGA的一些特性，例如低的NRE費用和重複配置來完成設計之功能。可結構化客製晶片由一些預製的電晶體，事先定義完成的金屬層，以及尚未定義的via 層（或少許的金屬層）組成。尚未定義的via 層是留給使用者來連接基本邏輯單元間的連線及基本邏輯單元內的電晶體連線。基本邏輯單元由基本單元組成。一個好的基本單元必須要有高電晶體使用率且可符合各種不同需求的設計。以此基本單元設計晶片時，若能減少設計晶片的開發工具更為重要。
在這篇論文裡，我們針對結構化客製晶片設計一類似標準元件之穿孔可程式化的查表基本單元，能夠運用現有的標準流程工具進行新晶片設計。我們根據查表基本單元轉換行為特性建造一函式庫分類方法。我們以此基本單元依照分類方法建立動態產生函式庫與先特徵化函式庫並介紹運用此基本架構之兩種晶片設計流程。運用我們的基本單元設計之電路在電路時間延遲上的誤差平均為2.26%。比較兩種函式庫在相同的時脈要求之下。動態產生函式庫電路比先特徵化函式庫少23%晶片面積。

關鍵字

查表 ； 函式庫 ； 可結構化

並列摘要

The popular IC design styles, standard cell design and FPGA, are facing a big challenge: attaining a proper balance between mask cost and performance. Structured ASIC retains some properties of standard cell designs such as higher performance and smaller area and also possesses some properties of FPGA such as low non-recurring engineering cost and re-configurability. It emerges as a good solution to the above challenge. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Moreover, it should also minimize the efforts of developing tools for chip designs. We propose two library creation methodologies based on the behavior of LUT switching characteristics. One is dynamically generated library, the other is pre-characterized library. Experimental results show that the timing error of out timing library is on average 2.26%. With the same clock period requirement, the numbers of instance are reduced on average by 23%, if a dynamically generated library is used.

並列關鍵字

LUT ； cell library ； structured ASIC

參考文獻

[2] Behrooz Zahiri, “Structured ASICs: Opportunities and Challenges,” ICCD, pp. 404-409, 2003.

[4] Kun-Cheng Wu, Yu-Wen Tsai, “Structured ASIC, Evolution or Revolution?, “ISPD, pp.103-106, 2004.

[5] J. Cong, and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.

[6] N. Jayakumar and S. P. Khatri, “A Metal and Via Maskset Programmable VLSI Design Methodology using PLAs,” ICCD, 2004, pp. 590–594.

[7] B. Hu, H. Jiang, Q. Liu, and M. Marek-Sadowska, “Synthesis and Placement Flow for Gain-Based Programmable Regular Fabrics,” ISPD, 2003, pp. 197–203.