使用多層次繞線器以增進於標準元件接腳上之雙倍鑽孔嵌入率

Improving Redundant Via Insertion Rate at Pins with Multilevel Router

曾威智(Wei-Chih Tseng)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2007年)

https://doi.org/10.6838/YZU.2007.00371

摘要

利用雙倍鑽孔來提昇晶片於製造時的良率及運作期間的可靠性是最有效的方式。 先前的研究在整體之鑽孔嵌入率上已獲得不錯的佳績。 然而最底層的鑽孔嵌入率卻始終低於平均。 為了研究此確切議題， 我們發展出一套追求嵌入率的且相容於商用的標準元件庫。
.重新設計一套標準元件庫之本意在於保留足夠的底層空間得以嵌入一份備援用的鑽孔相伴於原有的鑽孔， 但是由於商用的繞線器無法得知我們設計在元件資料庫接腳上的意圖， 因此本研究即是實作出一能判斷所有我們所設計於元件庫接腳上的意涵, 期望能達到最大的崁入率用來連接腳上的最底層鑽孔。
實驗結果顯示， 當我們的繞線器使用我們的元件庫時， 相較於使用商業界的元件庫， 平均而言獲得高達32%最底層鑽孔嵌入率的增進， 整體而言亦有9%左右的提升。
使用雙倍鑽孔的一大好處即是對整體效能沒有明顯的影響， 無論是時序上， 總繞線長度上皆得出此一結果。 足以見得雙倍鑽孔為一值得施行的措施。

關鍵字

多層次繞線器 ； 標準元件 ； 雙倍鑽孔

並列摘要

Appling redundant via(RV) insertion to a design is the most effective way for improving the manufacturing yield and circuits operating reliability.
Previous work has done great jobs that the insertion rate is wonderful enough except the lowest layer, via1. We figured out this problem that no one has ever mentioned before and developed a so called Double-Via(DV)-Driven standard cell library compatible with the commercial one(UMC018). Our intent to redesign a cell library is hoping that the insertion rate of on-pin-via1s can be increased by reserving the sufficient space for a redundant via insertion at all pins.
Because the commercial router can not understand our intention upon cell pins, we also implemented a so called DV-aware router embedded some awareness features dedicated for increasing insertion rate of via1 at pins.
Experimental results show that the DV-aware router importing our library can improve up to 32% via1 insertion rate in average against the commercial one. The average overall insertion rate also gains up to 9% improvement. Besides, there is no significant performance impact when vias are doubling.

並列關鍵字

Redundant Via ； Multilevel Router

參考文獻

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