應用FPGA於同步相量量測器設計之研究

A Study on the Design of Phasor Measurement Units Using FPGA

蔡政哲(Zheng-Zhe Cai)

指導教授 ： 林穎宏

長榮大學/資訊暨工程學院/資訊管理學系(所)/碩士(2011年)

https://doi.org/10.6833/CJCU.2011.00076

摘要

同步相量量測單元為智慧電網中最重要的量測元件，其使用全球定位系統所提供之1PPS與時間標籤以達取樣時間同步。台電現今使用之ADX3000 PMU中，同步時脈產生器是由離散的SSI數位IC所組成，可靠度不佳與體積龐大，且只有16 MB DRAM以儲存取樣資料，應用於智慧電網中已顯不足。
本文應用FPGA實現PMU中的同步時脈產生器與雙埠64 MB SDRM控制器，可使新型PMU達硬體整合、體積縮小與記憶體擴充之功能。設計之同步時脈產生器可補償外接振盪器之誤差，將同步時脈的最大同步誤差維持在0.1微秒內；雙埠SDRM控制器之一埠提供A/D轉換器將取樣值儲存於64 MB SDRAM，另一埠則提供PMU中的數位訊號處理器進行取樣資料的存取。應用所設計之FPGA於新型的PMU中可提升其效能與可靠度。

關鍵字

智慧電網 ； 同步相量量測單元 ； 同步時脈產生器 ； 雙埠SDRAM控制器 ； FPGA

並列摘要

Synchronized Phasor Measurement Units (PMUs), that use 1PPS (1 Pulse Per Second) and time marker provided by Global Positioning System (GPS) to synchronize the sampling time, are the most important components for measurement in the Smart Grid. Nowadays, the ADX3000 PMUs deployed in Tai-power systems use discrete SSI ICs to implement the synchronized clock generator. Therefore, the reliability is poor and the volume is bulky. Moreover, only a 16 MB DRAM is used to store sampling data in ADX3000 PMUs, so it is inadequate for the requirement in measurement for Smart Grid.
In this thesis, to integrate the hardware, reduce the volume and extend the storage capability for advanced PMUs, a synchronized clock generator and a dual-port SDRAM controller are designed and implemented in a FPGA. The designed synchronized clock generator can compensate the errors of synchronism, caused by frequency drift of an external oscillator, and maintain the maximum error within 0.1 μs. For the dual-port SDRM controller, one port is for A/D converter to store sampling data in a 64 MB SDRAM, and the other port is for the digital signal processor to access sampling data for computations. Applying the designed FPGA to advanced PMUs can increase performance and reliability.

並列關鍵字

Smart Grid ； PMUs ； synchronized clock generator ； dual-port SDRAM controller ； FPGA

參考文獻

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