具有製程、電壓、溫度不敏感性電壓-時間-電壓轉換器之十二位元二階雜訊塑形連續漸進式類比數位轉換器

A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter

陳志誠(Chih-Cheng Chen)

指導教授 ： 謝志成

國立清華大學/電機資訊學院/電機工程學系所/碩士(2021年)

摘要

本論文提出一個具有製程、電壓、溫度不敏感性電壓-時間-電壓轉換器之十二位元二階雜訊塑形連續漸進式(successive-approximation register, SAR)類比數位轉換器(analog-to-digital converter, ADC)。
本論文使用了電壓-時間-電壓(Voltage-Time-Voltage, V-T-V)轉換器提供了精準的開環增益，由於僅依靠電容與電流比例，其增益本質上對於製成、電壓與溫度(Process-Voltage-Temperature, PVT)具有不敏感性，因此並不需要教正即可實現理想的雜訊轉換函數 (noise transfer function, NTF)。此外，V-T-V轉換器只消耗動態功率。透過使用元件比例設計與動態功耗方式，所提出的ADC具有抵抗PVT變異與良好功率效益的特性。
為了驗證本電路，此架構使用90奈米1P9M互補式金氧半導體製程製作，核心電路面積為429.7 x 90.7um2，在1伏特電源電壓及1千萬赫茲取樣頻率操作下，此晶片在625千赫茲輸入頻寬實現之SNDR為73.8dB，其對應的ENOB為12-bit，功率消耗為71.4微瓦，而等效的Walden figure of merit (FOMW)為14.2fJ/conversion-step，Schreier figure of merit (FOMS)為173.2dB。

關鍵字

過採樣 ； 雜訊塑形 ； 連續漸進式類比數位轉換器

並列摘要

This thesis presents a 12-ENOB second-order noise shaping successive-approximation register (NS SAR) analog-to-digital converter (ADC) with PVT-insensitive voltage-time-voltage (V-T-V) converter.
The proposed NS SAR ADC uses the V-T-V converter to provide an accurate open-loop gain stage for active residue process. By relying on the capacitor and current ratio only, the gain of V-T-V converter is inherently PVT-insensitive. Therefore, no calibration is needed and an aggressive noise transfer function (NTF) can be realized. Moreover, the V-T-V converter consumes only dynamic power. By using ratio design and dynamic manner, the proposed ADC is PVT-insensitive and energy efficient.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 429.7 x 90.7um2. At 1V supply voltage and 10MS/s sampling rate, the ADC achieves the SNDR of 73.8dB and the corresponding ENOB is 12-bit at the input bandwidth of 625kHz. It consumes 71.4µW power totally, resulting in the Walden figure of merit (FOMW) of 14.2fJ/conversion-step and Schreier figure of merit (FOMS) of 173.2 dB, respectively.

並列關鍵字

oversampling ； noise-shaping ； SAR ADC

參考文獻

[1] B. Murmann, "ADC Performance Survey 1997-2021," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.

[2] W. Guo, H. Zhuang and N. Sun, "A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators," 2017 Symposium on VLSI Circuits, 2017, pp. C236-C237.

[3] H. Zhuang et al., "A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting," in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1636-1647, June 2019.

[4] Y. Hwang, Y. Song, J. Park and D. Jeong, "A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS," 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018, pp. 247-248.

[5] S. Li, B. Qiao, M. Gandara and N. Sun, "A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 234-236.