用於轉換錯誤之掃描鏈內建自我測試電路編譯器

A Scan-based Transition Fault BIST Compiler

詹欣達(Hsin-Ta Chan)

指導教授 ： 劉靖家

國立清華大學/電機資訊學院/電機工程學系/碩士(2009年)

https://doi.org/10.6843/NTHU.2009.00061

摘要

BIST is an attractive approach to test delay faults due to its support for at-speed test. In order to get high quality test patterns with least built-in hardware overheads, an algorithm is proposed to design high fault coverage LFSRs and reseeding logic as a test pattern generator of a transition fault scan-based BIST. This BIST architecture is designed for at-speed testing with launch-off-capture test scheme. By incorporating a probability-based estimator and a fast fault simulation in a simulated-annealing based framework, we can select one high-quality LFSR as the test pattern generator. For the remaining hard-to-detect faults, test patterns are generated using a specialized ATPG model for scan-based BIST. Then another search process is then invoked to select high fault coverage seeds for the LFSR from the deterministic test patterns. The constructed hardware LFSR generator can increase the pseudo-random fault coverage without any additional overheads. Also the selected seeds can generate the same deterministic fault coverage of ATPG with only 5.75% of the original test pattern numbers. Additionally, the overall scan-based BIST insertion flow is compatible with the standard cell-based design flow.

關鍵字

內建自我測試

並列摘要

對於測試轉換延遲錯誤 (transition fault)，內建自我測試電路 (BIST) 是一個不錯的方法，因為它可以支援全速測試 (at-speed test)。為了獲得高品質的測試樣本 (test pattern)，我們提出了一個演算法，設計出高錯誤涵蓋率 (fault coverage) 的線性反饋位移暫存器 (LFSR) 和種子置換邏輯電路 (reseeding logic)，作為測
試轉換延遲錯誤的以掃描鏈為基底的內建自我測試電路 (scan-based BIST) 的測試樣本產生器。這個內建自我測試電路架構是用launch-off-capture 的方式來做全速測試。藉由合併以機率為基礎的錯誤估計和快速的錯誤模擬到以模擬降溫法 (Simulated Annealing) 為基礎的架構內，我們可以挑選一個高品質的線性反饋位移暫存器作為測試樣本產生器。對於剩下來的難以被測到的轉換延遲錯誤，我們使用專門用於以掃描鏈為基底的內建自我測試電路的自動測試樣本產生器 (ATPG) 模型來產生決定性的測試樣本。接著，使用另一個搜尋程序從決定性的測試樣本之中，挑選出高錯誤涵蓋率的種子給線性反饋位移暫存器作為初始值使用。被建構出來的線性反饋位移暫存器硬體電路可以不用花費任何額外的成本，而增加虛擬亂數測試樣本的錯誤涵蓋率。除此之外，被挑選出來的種子可以達到和自動測試樣本產生器模型相同的決定性的測試錯誤涵蓋率，卻只需要儲存原本5.75%的測試樣本數。最後，我們所提出的以掃描鏈為基底的內建自我測試電路的產生流程可以完全融入標準的以細胞為基底的設計流程 (cell-based design flow) 之中。

並列關鍵字

built-in self test ； scan-based BIST

參考文獻

[3] N. A. Touba and E. J. McCluskey, “Bit-fixing in pseudorandom sequences for scan BIST,”

pp. 545–555, Apr. 2001.

Conference on Computer-Aided Design, 1996.

[5] N. Z. Basturkmen, S. M. Reddy, and J. Rajski, “Improved algorithms for constructive multiphase

[7] C.-A. Chen and S. Gupta, “Design of efficient BIST test pattern generators for delay testing,”