- 學位論文
用於傳輸錯誤內建自我測試之最佳化線性反饋位移暫存器及種子轉換電路
Optimization of LFSRs and Reseeding Logics for Transition Fault BIST
摘要
提出一個可以設計出高錯誤涵蓋率的線性反饋位移暫存器(Linear Feedback Shift Register, LFSR) 和種子轉換電路當作傳輸錯誤內建自我測試電路(Built-in Self Test, BIST)的測試樣本產生器。首先，我們用模擬降溫法( Simulated Annealing, SA)來搜尋出高品質的線性反饋位移暫存器然後利用我們提出的轉換種子方法來提高錯誤涵蓋率。在模擬降溫法過程中需要評估線性反饋位移暫存器很多次。所以我們發展出以機率為準的評估器和快速的錯誤模擬加入在模擬降溫法的架構中。如此一來，我們可以快速地選出一個高品質的線性反饋位移暫存器來偵測電路的傳輸錯誤。針對剩下來難以被測到的錯誤，將由特殊的自動樣本產生器(Automatic Test Pattern Generator, ATPG)來產生測試樣本。接著是從這些測試樣本中選出可以達到高錯誤涵蓋率的當作線性反饋位移暫存器的種子的搜尋方法。在我們的實驗結果中，我們所找出的線性反饋位移暫存器硬體架構在不增加多餘的面積的情況下可以多增加到3%的錯誤涵蓋率。同時我們所選的種子可以達到跟決定性的錯誤涵蓋率一樣高的值，但僅只使用到1.1%的決定性的測試樣本。
關鍵字
內建自我測試電路並列摘要
An algorithm is proposed to design high fault-coverage LFSRs and reseeding logic as a test pattern generator of a transition-fault BIST. First, we develop a simulated annealing (SA) algorithm to search a high-quality LFSR and then using our proposed reseeding method to increase the fault coverage. In our SA process, there are many times to estimate LFSRs. So we develop a process incorporating a probability-based estimator and a fast fault simulation in simulated annealing framework. Therefore, we can select fastly one high-quality LFSR for detecting the transition faults of a circuit. For the remaining hard-to-detect faults, test patterns are generated with a specialized ATPG model. Another search process is then invoked to select high fault-coverage seeds for the LFSR from test patterns. The constructed hardware LFSR generator can increase the pseudo-random fault coverage as much as 3.26% without any additional overheads. Also the selected seeds can generate the same deterministic fault coverage with only 1.1% of the original test patterns.