應用於錯誤地板估算之縱向式低密度奇偶檢查解碼器架構

A Shuffled LDPC Decoder Architecture for Error-Floor Evaluation

陳楚天(Chen, Chu Tian)

指導教授 ： 翁詠祿

國立清華大學/電機資訊學院/通訊工程研究所/碩士(2015年)

摘要

現有一系列用高碼率，長碼長之校驗矩陣定義的低密度奇偶檢查碼。我們想觀察這些矩陣使用縱向式解碼的模擬結果，如使用軟體測試，想跑到發生錯誤地板(error floor)的資料點將耗費上萬天的模擬時間。為節省模擬時間，本論文將採用硬體的方式來測試，將縱向式解碼器用電路實現後，將其掛載到FPGA平台測試。但如採用傳統縱向式解碼器電路架構，其電路面積會過大，所占用的資源將超過FPGA板所提供的。為解決此問題，本論文採用了降低解碼器平行度的方式，在此使用新的排程法來達成目的，此排程法取名為折線排程，解碼器的面積將下降27%。此外，為加快FPGA驗證速度，本論文提出了預先載入(preload)的技術來減少解碼迭代次數以加快解碼器吞吐量。於高SNR的資料點，吞吐量25%至33%。

關鍵字

低密度奇偶檢查碼 ； 縱向式解碼器 ； 排程 ； 預先載入 ； 現場可程式化邏輯閘陣列

並列摘要

It will take a long time to obtain error-floor results of Low-Density Parity Check Codes using software simulation. To shorten the simulation time, this paper uses FPGA-based emulation to evaluate the error-floor performance. Shuffled LDPC decoder is implemented using FPGA. The conventional shuffled decoder architecture is very large so that the FPGA resource is not enough. We reduce parallelism of the decoder to solve this problem. This paper proposes a new schedule method to achieve this goal. Approximate 27% of the total area is reduced. In addition, we propose a new preloading technique to increase throughput of the decoder. This new technique can provide an increased throughput so that the shorter simulation times can be achieved.

並列關鍵字

LDPC ； Shuffled Decoder ； schedule ； preload ； FPGA

參考文獻

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