低功耗智慧型影像感測器與高速數位時間延遲積分影像感測器之研究與發展

The Research and Development of CMOS Imagers for Low-Power Smart Functions and High-Speed Digital Time-Delay-Integration Operation

殷勤(Yin, Chin)

指導教授 ： 謝志成

國立清華大學/電機資訊學院/電機工程學系所/博士(2017年)

摘要

在本論文中，首先會介紹CMOS影像感測器的市場、應用與基本電路架構發展。接著進入我第一個晶片設計，一個低功耗高動態範圍的智慧型影像感測器。依序介紹其研究動機和目標應用，然後是此晶片重要的特色，接著是電路的架構與操作，然後講解晶片量測並給一個小結。其後講到我的第二個晶片設計，一個高速數位式時間延遲積分影像感測器，相同的會依序介紹應用背景，規格推導與時間延遲積分的概念，然後帶到電路的架構與操作，接著講解晶片量測並給小結。最後是本論文結論與未來發展。
我們設計了一個擁有多種操作模式的智慧型影像感測器，包含了邊緣擷取、多點追蹤和高動態範圍影像等模式，其目標為在物聯網應用中架設無線感測網路。我們設計的像素包含了一個可操作於0.5伏之脈衝寬度調變感測器，其功能兼顧高動態範圍光電反應與固定圖像雜訊壓抑。借由局部像素間回饋網路、像素內低功耗動態邏輯與事件驅動接力讀出之對應週邊，我們可以實現陣列平行化影像訊號處理。我們使用台積0.18微米金氧半導體影像感測器製程來設計，製作了一個64乘64陣列大小的原型晶片。在多點追蹤模式時，量測到的追縱速度為14.28kfps、追蹤誤差為0.36像素而最大追蹤點數為四點。在高動態範圍影像模式時，量測可達到96.7dB之動態範圍。
我們設計了一個512行高速線性掃描影像感測器，其使用了32級數位時間延遲積分操作。感測器的訊號處理架構由類比前端電路、類比數位轉換器和數位累積器所組合而成，其設計為了操作速度、晶片面積和功耗效率來最佳化。我們設計了一個8行共享的十位元連續漸進類比數位轉換器並使用資料預測切換技術，配合著11位元的數位累積器在32級時間延遲積分操作下可以達到15位元資料長度。此晶片在32級時間延遲積分操作下可以提升訊雜比14.84dB，我們使用台積0.11微米背照式金氧半導體影像感測器製程來設計此線性時間延遲積分感測器，其操作掃描時間為104μs、像素大小為7.5μm而功耗為153.2μW/column。相較於其他已提出的晶片成果，我們提出的影像感測器於系統最佳化考量上更有競爭力。

關鍵字

互補式金氧半導體影像感測器

並列摘要

In this thesis, I first introduce the market, the applications and the fundamental circuit architecture development of CMOS image sensor (CIS). And then I present my first IC work: “a low-power high dynamic range smart CIS”, which includes the research motivations and target applications, the key features, circuit descriptions and the measurements with summary. Next I demonstrate my second IC work: “a high-speed digital time delay integration (TDI) CIS”, which includes background, specifications, TDI concept, circuit descriptions and the measurements with summary. At the end of this thesis, I conclude these two works and explain the future works.
A smart image sensor is designed with multiple operation modes including edge extraction (EE), multi-point tracking (MPT), and high-dynamic-range (HDR) imaging for wireless sensor nodes in internet-of-things (IoT) applications. The pixel consists of a 0.5 V operated pulse-width-modulation (PWM) sensor for achieving high dynamic range (HDR) response and low fixed pattern noise. Array-level image signal processing is implemented by using a local inter-pixel feedback network, in-pixel low power dynamic logics, and a corresponding peripheral with an event-driven hand-shaking readout. A prototype chip with a 64 × 64 CIS array is designed and fabricated in TSMC 0.18-μm CIS technology. In MPT mode, the measured tracking speed is 14.28 kfps with an error of 0.36 pixels and a tracking capability up to four-point. In HDR imaging mode, the achieved dynamic range is 96.7 dB.
A 512-column high-speed linear scan image sensor is designed with 32-stage digital time-delay-integration operation. A signal processing architecture consists of analog front end (AFE), analog-to-digital converters (ADC), and digital accumulators (DA) are designed with optimization of timing, area, and power efficiency. An 8-column-shared 10b SAR ADC with data prediction switching (DPS) technique and 11b DA are proposed to achieve a data depth of 15 bit after 32-stage TDI. The achieved signal-to-noise ratio (SNR) boost is 14.84dB after 32-stage TDI operation. The proposed linear TDI sensor is implemented in 0.11-μm TSMC backside illumination (BSI) CIS technology with a line time of 104μs, a pixel pitch of 7.5μm, and a power consumption of 153.2μW/column. Compare with the state-of-the-art designs, the proposed image sensors are more competitive in system optimization.

並列關鍵字

CMOS Image Sensor

參考文獻

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