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  • 學位論文

具平均電壓值回授與溫度補償之時脈產生器

CMOS Relaxation Oscillator with Voltage Averaging Feedback and Temperature Compensation

指導教授 : 徐永珍

摘要


現在的電子產品中,只要有時序控制的電路,都需要時脈訊號才會運作。時脈訊號的精確度決定了電路的工作穩定度。因此,如何產生一個穩定頻率的時脈訊號,是近年來的重大課題之一。現在大部分的時脈訊號都是由石英振盪器所產生,主要是因為石英為目前頻率穩定度最高的振盪元件。然而,石英晶體有大面積、高功率消耗,及無法與CMOS製程做整合等缺點,因此過去幾十年來無論學界專家或公司研究團隊都試圖尋找能替代石英振盪器的方案。 近年來被提出取代石英振盪的方法有MEMS振盪器、FBAR振盪器,及CMOS振盪器。但是,MEMS與FBAR的製程技術困難,無法與CMOS電路整合;而CMOS振盪器因半導體特性易受環境影響,導致其振盪頻率會因工作溫度與供應電壓的變動而改變。也因此,到目前為止石英振盪器還無法完全被取代。不過,CMOS電路在設計上可加上適當的補償方式將穩定度提高,因此我們致力於CMOS振盪器,以標準製程下實現低功率消耗、具溫度補償的時脈產生器。 本篇論文提出具有優良溫度補償的CMOS時脈產生器,使其振盪頻率對溫度的變異極低。此外,透過只有一組充放電路路徑與除頻器,達到較低的頻率抖動程度(Jitter)與工作週期(Duty Cycle)接近50%的效果。此晶片使用 TSMC 0.18 μm 1P6M標準製程實現。

並列摘要


Clock signal is essential for any electronic circuits that require timing control. How to generate an accurate and stable clock signal becomes one of the most important issues. Nowadays most clock signals are generated by crystal oscillators primarily because of their excellent stability. However, in view of the drawbacks of quartz crystal such as large size, high power consumption, and being unable to be integrated into microelectronic process technology, for several decades, researchers had been exploring other technologies in order to replace quartz oscillators. Recently, some methods such as MEMS, FBAR and CMOS oscillators were proposed. Unfortunately, MEMS and FBAR oscillators need complex and costly processes to realize and they still cannot be integrated with CMOS circuits. The characteristics of Si devices are easily influenced by the changing variables of the environment, leading the frequency of CMOS oscillators to be sensitive to temperature and supply voltage. These are the reasons why crystal oscillators still cannot be replaced so far. For CMOS oscillators, luckily, we can add some proper compensation to improve their stability. Thus, we tried to develop a CMOS oscillator with low power consumption and high temperature stability. In this paper, a CMOS relaxation oscillator which is nearly insensitive to temperature variation is proposed. In addition, by using single charging and discharging path and a frequency divider, low jitter and nearly 50% duty cycle were achieved. This chip has been realized in the TSMC 0.18 μm 1P6M process.

參考文獻


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