3D Interconnect Capacitance Modeling for Off-Chip High-Performance Designs

當製程越來越小時，許多的公司為了增加它們的良率，都努力的研究怎樣增加系統單晶片(System-on-Chip)和單封裝系統(System-in-Package)上金屬線的訊號完整性。現在來說，系統單晶片和單封裝系統重要的金屬連接線都非常的重要。單封裝系統包含了拉線和印刷電路板，它有一些優點，例如：成本較低、time-to-market較短、比較有效率和風險性較低；而系統單晶片的效能較好。但它們兩個都有個趨勢就是，越來越小且頻率越來越高。因此，設計者必須面對到一些問題且必須去解決它，像是寄生效應和傳輸線效應。寄生效應是常見的訊號完整性的問題，而當頻率增加且連接線的尺寸變小時，我們就要考慮到傳輸線效應，把連接線的模型從集總模型(lumped model)變成散佈式模型(distributed model)。寄生電容是寄生參數 (RLCKG) 的其中一種，它在低頻和高頻都扮演著重要的角色，它使得連接線必須多花時間去傳送訊號，這樣也許會讓設計不符合預期。而電容抽取通常需要考慮到週遭的環境，不像電阻通常只需考慮到自己本身的金屬線，而電感則考慮到return path。如果我們不能正確的抽取電容，將會得到低的良率。現在來說，市面上的商業軟體對於抽取on-chip的連接線電容已經算滿成熟的且假設金屬線的模型是集總模型。而3D的電容又需要被考慮到，要描述整個結構的輸入檔給解電場軟體也是不太方便，且抽取也是耗費時間的。基於以上的原因，在本論文中，我們提出了一個方法，使用3D解電磁場軟體(Raphael)對四層與兩層印刷電路板的金屬連接線建立電容的表格並寫了一個查表的程式可以從電容表格得到散佈式的電容。每條重要金屬連接線的電容表格可能不一樣，所以查表程式會依據使用者輸入的金屬線結構和參數去找到相對應的電容表格，然後做內插動作來取得電容值。這個有效率的方法將使設計者快速的得到散佈式的電容，而不是集總電容。

關鍵字

系統單晶片；單封裝系統；印刷電路板；寄生電容；傳輸線效應；散佈式模型；解電場軟體；內插

並列摘要

As technology process getting smaller and smaller, many companies make effort in signal integrity of SoC (System-on-chip) and SiP (System-in-Package) interconnects in order to improve the yield. Both SoC and SiP are critical now, compare SoC with SiP, SiP includes wire bond and PCB, it has many advantages, such as lower cost, short time-to-market, efficient, and low-risk, while on-chip has better performance. But they both have a trend that they are getting smaller and smaller with higher frequency. Thus, there are some problems should be solved by designers, like parasitic effect and transmission line effect. Parasitic effects are common issues of signal integrity. When frequency increases and the interconnect size decreases, we should make the interconnect model from lumped to distributed to take the transmission line effect into account. Parasitic capacitance is one of the parasitic parameters (RLCKG). It plays an important role both on low and high frequency and it makes interconnect consume more time to transmit the signal. This results in an unexpected performance of the designs. Capacitance extraction often needs to consider the ambient environment, while resistance extraction often considers only the target interconnect and inductance extraction considers the return path. If we can’t extract the capacitance accurately, we will get lower yield. Nowadays, the commercial tools for on-chip interconnect capacitance extraction are so mature and they assume their models to be lumped models. Also, the 3D capacitance extraction is needed, but it is inconvenient for us to describe an overall PCB structure and it takes a lot of time to extract the capacitance for the overall structure. Due to the above reasons, in this thesis, we propose a method to use the 3D field solver (Raphael) to build capacitance tables for common interconnect of printed circuit board and write a look up table program to get the distributed capacitance from tables. Each critical net may need different tables. So, according to the trace case and parameters user entered, the look up program will find the corresponding table and do interpolation to get capacitance. This efficient way will help designers to quickly get distributed capacitance, not a lumped one.

並列關鍵字

SoC ； SiP ； Printed Circuit Board ； Parasitic Capacitance ； Transmission Line Effect ； Distributed Models ； Field Solver ； Interpolation

參考文獻

[4] RAPHAEL User’s Manual, Version 2003.09, 2003.

electromagnetic modeling of system-in-package and system-on-glass”

[6] Keh-Jeng Chang et al., “HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs”, Hewlett-Packard Company, Palo Alto, CA 94304, USA.

[7] “International Technology Roadmap for Semiconductors" http://public.itrs.net

[8] “National Applied Research Laboratories National Chip Implementation Center”, http://www2.cic.org.tw

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3D Interconnect Capacitance Modeling for Off-Chip High-Performance Designs

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