功率適應方法之設計與評估

Design and Evaluation of a Power-Adaptive Methodology

莊孝安(Hsiao-An Chuang)

指導教授 ： 黃稚存

國立清華大學/電機資訊學院/資訊工程學系/碩士(2008年)

摘要

近幾年來，功率或能源消耗問題逐漸在VLSI設計上受到重視。動態電源管理 （DPM) 是有效節省能源的設計方法之一，它根據系統或使用者的需求來調整工作電壓和工作頻率。藉此，在滿足效能條件下降低能量的使用，因而避免電路過熱所造成系統不穩定的問題。尤其在手持系統上，透過DPM可以大幅延長電池的工作時間。 然而在電路設計時，我們無法有效預測將來系統或使用者的需求變化，這種特性下增加DPM的複雜度。常見的設計方式通常透過機率模組來實現DPM，然而這個方法比較適合透過軟體來設計。在本篇論文中，我們提出一個動態電源管理系統之設計，此設計包含了動態電源管理者、時脈產生器、電壓調整器和具有非同步介面的AES加密器。此外，我們透過波氏 （Poisson) 分佈來描述不固定的系統需求，同時依據成功量測的具功率意識AES加密器晶片特性來真實描述我們系統模組。實驗結果顯示出我們提出的電源管理機制可以有效管理AES加密器的能源，此設計方法，在將來可以廣泛應用在通訊或安全領域設計上。

關鍵字

電源管理 ； 功率意識 ； 先進加密標準

並列摘要

Power or energy has become one of the most urgent issues in VLSI designs in recent years.
Dynamic power management (DPM) can alter the power level of the system/components
during the runtime, preventing from the overheating of the circuit, and also prolonging
the battery life for portable systems. However, the non-stationary characteristic of the
workload, which is usually not predictable in the design phase, makes the DPM patterns
and applications dependent by nature. Traditional DPM relies on complicated statistics and
probability models, which are suitable only for high-level software implementation.
In this thesis, an approach for the power-adaptive design methodology is presented. Our
power adaptive system consists of behavior-level and RTL components. The host, dynamic
power manager, clock generator, and the voltage regulator with realistic parameters are mod-
eled in SystemC, whereas the AHB bus wrapper and the target example, AES crypto-engine
with asynchronous interface, are the RTL designs. In addition, the non-stationary requests
are modeled as a stochastic Poisson process. And the proposed power manager features
a workload-driven policy to monitor the incoming AES requests. Considering the realistic
characteristics of clock generator and voltage regulator when changing the frequency and
power, the performance and energy trade-o® can be explored and evaluated by using our
system-level simulation environment. The experiment results show that our power adap-
tive approach can provide high energy e±ciency and about 52% energy saving on average.
The architecture is simple and e®ective for the hardware implementation. Our approach
can be easily adopted for other data-intensive processing elements such as cryptographic
accelerators, digital signal processing units, and communication modules, etc.

並列關鍵字

DPM ； Power-aware ； AES

參考文獻

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