機器學習技術應用於系統性製程變異特徵之辨認方法

Feature Identification of Systematic Process Variations with Machine Learning Techniques

許碩祐(Shuo-You Hsu)

指導教授 ： 劉靖家

國立清華大學/電機資訊學院/電機工程學系/碩士(2012年)

摘要

隨著互補式金屬氧化物半導體製程技術進入深次微米時代，製程變異對於產品良率影響越趨嚴重。為了辨認製程變異不確定性所造成的低良率原因，製程監控電路，例如: 環型震盪器、延遲鏈或者是以延遲錯誤測試為基礎的診斷方法被應用於量測晶片因為製程變異所引起的額外元件延遲。依據所量測到的元件延遲資訊，本論文提出了一套方法進一步地區分不同的製程變異所造成的影響並辨認引起製程變異的主要設計特徵 (即最有可能引起製程變異的原因，例如：邏輯閘種類)。此結果可以回饋給電路設計者與製程工程師，進而快速修正電路設計或調整製程參數以克服製程變異所造成的影響且有效地提升產品的良率。

在本論文中，我們提出一套自下而上 (bottom-up) 分析方法，首先將晶片依據實體位置切分成數個子區塊。使用支持向量回歸法 (support vector regression) 建構製程變異模型，並逐步地合併子區塊如果製程變異的行為可以被相同製程變模型所解釋，此方法可以有效的區分不同製程變異的影響與其影響的範圍。而後，使用機器學習領域中的特徵萃取演算法分析並排序電路的特徵。越高排序的特徵代表越有可能是引起製程變異的主要原因。

實驗結果顯示，本論文所提出的方法可以有效地辨認不同的製程變異影響區域並且能找出引起製程變異的主要特徵。

關鍵字

超大型積體電路 ； 系統性製程變異 ； 機器學習

並列摘要

As the CMOS technology coming to nano meter scale, process variation play an important role in yield of production. In order to identify variability issues for low yield process, process monitoring circuitry, such as ring oscillators, delay chain, or delay-test-based diagnosis methods are applied to measure excessive delays in a circuit. Based on the observed delay data, we propose to further classify and find the main features (most possible causes, e.g., gate types) that would explain the severity of a particular process region. Then fed back information to designers and process engineers. That can help them rapidly tune design or adjust process parameter to overcome the issue caused by process variation and promote the yield of production.

In our method, support vector regression is employed to build models and partition the circuit into different process regions. That can distinguish different process variation influence and its affected regions. Then feature extraction algorithm in machine learning field is applied to rank features. The feature with higher rank, means it have more probability to cause process variation.

Experimental results show that the proposed method can effectively identify process regions and rank injected variations.

並列關鍵字

VLSI circuits ； Systematic Process Variations ； Machine Learning

參考文獻

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Dept. EECS, Massachusetts Institute of Technology, 2001.

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cmp for on-chip interconnect optimization”, IEEE Transactions on Electron Devices, vol. 51,

[3] Y.-Y. Chen and J.-J. Liou, “A non-intrusive and accurate inspection method for segment delay