- 學位論文
新型垂直式CMOS加速度感測器之研製
A Novel Design for CMOS Capacitive Vertical Accelerometer
摘要
本研究提出ㄧ利用化學電漿蝕刻的新型CMOS後製程技術，此製程是讓反應氣體在較低的真空度下，其平均自由徑較短，因而增加了側向蝕刻能力，蝕刻結果趨近於等向性的蝕刻效果，而側向蝕刻能力可以由反應腔體的真空度來控制。除此之外，利用化學電漿蝕刻的CMOS後製程可以去除遮罩下方的二氧化矽，因此在CMOS微結構的垂直方向可以製作出類似對稱的堆疊結構，用這對稱的結構可有效的抑制CMOS多層結構的殘留應力問題。更進ㄧ步，這個後製程也可以製作CMOS單層金屬結構，如微彈簧。而以單層金屬結構所製作的微彈簧其彈性係數非常的低，可以有效的增加CMOS感測器的靈敏度。 本研究利用一平行板電容之CMOS垂直加速度計來驗證此新型的後製程概念，量測結果指出，在500 μm × 500 μm 的CMOS結構下，翹曲高度小於2 μm，而垂直的CMOS加速度計靈敏度為3.2 mV/g，系統的噪聲約10 μV / √Hz。
並列摘要
This study presents a novel fabrication process of post-CMOS (complementary metal oxide semiconductor) with the chemical plasma etching. To release the CMOS microstructures, the shorter mean free path to increase lateral etching can be employed in the rough vacuum. The etching profile trends isotropy and the capability of lateral etching are controlled by pressure of the chamber. In addition, the chemical plasma etching can release silicon dioxide under the mask. This approach can fabricate symmetric geometry in the vertical direction to decrease the effect of CMOS–MEMS residual stress. Moreover, the thin single metal layer structures also can be fabricated by chemical plasma etching such as micro-spring. It has the characteristics of the lower spring constant to increase the displacement of the proof mass. Thus, the sensitivity can be further improved. A parallel-plate capacitive vertical CMOS accelerometer is demonstrated in this new concept of post-CMOS process. Based on this approach, the measured results show the residual stresses effect can be minimized in CMOS multilayer microstructures, and furthermore the curl-up effect of flat-plane is less than 2 µm across the 500 μm × 500 μm area. The sensitivity of the vertical CMOS accelerometer is about 3.2 mV/g, and total noise floor is 10 μV / √Hz.