Design of CMOS RF Transmit/Receive Switch and Low Noise Amplifier

互補式金氧半射頻收發切換開關及低雜訊放大器之設計

朱浚學(Chun-Hsueh Chu)

指導教授 ： 黃智方 ； 龔正

國立清華大學/電機資訊學院/電子工程研究所/博士(2009年)

https://doi.org/10.6843/NTHU.2009.00150

摘要

本論文目的在於研究以互補式金氧半場效電晶體來設計高功率、低損耗之射頻收發切換開關及探討主動電感在射頻低雜訊放大器之應用。論文中共提出了900-MHz、 Wide-band(2-GHz to 5.8-GHz)與 DC-10 GHz broadband三種射頻收發切換開關。此外，吾人提出堆疊式的架構、高基板隔離度及電晶體基體浮接等技巧以改善射頻收發切換開關之功率處理能力並降低損耗。吾人利用商用標準0.18-um的互補式金氧半製程設計的900-MHz之射頻收發切換開關可達到30 dBm的P1dB，1.0 dB的穿透損耗及35.2 dB的隔離度。而 Wide-band射頻收發切換開關在5.8 GHz可達到27 dBm的P1dB、1.28 dB的穿透損耗及24 dB的隔離度。DC-10 GHz broadband 射頻收發切換開關在10 GHz可達到27 dBm的P1dB、1.69 dB的穿透損耗、小於 -15 之 S11 與S22 參數值。
另外，吾人研製主動電感以應用於無線區域網路，我們選擇將主動電感耦合於5.7-GHz低雜訊放大器之源極端以增加線性度並達到縮小晶片面積的目的。此電路在5.7-GHz的量測特性如下：小訊號增益為17 dB，雜訊指數為3.4 dB，線性度 (IIP3) 達 -7 dBm。

關鍵字

射頻 ； 互補式金氧半 ； 開關 ； 低雜訊放大器 ； 主動電感 ； 收發器

並列摘要

This thesis presents comprehensive methods for the design of RF CMOS Transmit/Receive switch with high power-handling capability and low insertion loss. Techniques such as RF floated body to extend the bandwidth and decrease the insertion loss, and stacking architecture with high substrate isolation to enhance the power-handling capability are used for the design of the T/R switch on a standard 0.18um triple-well CMOS process. The measured performance of the T/R switch designed at 900-MHz demonstrates the effectiveness of the methods presented in this dissertation such that insertion loss less than 1 dB, isolation up to 35.2 dB, and input 1-dB compression point of 30-dBm can be achieved. Besides, insertion loss less than 1.28-dB, isolation higher than 24 dB, and input 1-dB compression point of 27-dBm can be achieved for the switch designed at 5.8-GHz. The switch designed for DC-10 GHz applications can reach insertion loss less than 1.69 dB, with S11 and S22 smaller than -15, and input 1-dB compression point of 27-dBm.
Moreover, this dissertation presents a novel application of the active inductor in the design of the low noise amplifier (LNA). To reduce the silicon area consumed by the LNA without sacrificing its linearity, the passive source-degenerated inductor in the conventional design is replaced with the active inductor. The LNA is fabricated with a standard 0.18-um CMOS process. Compared with previous arts, this LNA exhibits good figure of merit (FOM) based on its power consumption of 19 mW, measured power gain of 17 dB, input third-order intercept point of -7 dBm, and noise figure of 3.4 dB at 5.7-GHz.

並列關鍵字

RF ； CMOS ； switch ； LNA ； low noise amplifier ； transceiver

參考文獻

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