晶片尺寸封裝於板層級掉落測試之不確定性與可靠度分析

Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test

佐野雅文(Masafumi Sano)

指導教授 ： 江國寧

國立清華大學/工學院/動力機械工程學系/碩士(2009年)

摘要

現今之電子產品的市場趨勢逐漸朝微小化、輕量化以及多功能的方向發展。然而，於日常生活中，因其攜帶方便而使人為攜帶時的疏忽造成電子產品的掉落或是碰撞的機率大幅提升，故針對電子產品與其內部封裝元件之掉落測試研究逐漸受到重視與要求。電子元件工業聯合會（Joint Electron Device Engineering Council, JEDEC）所提出的印刷電路板階級掉落試驗（Board-Level Drop Test）之測試方法已被眾多研究單位採用來評估封裝元件之抗衝擊能力。但是，此規範容易受到測試條件的改變而影響實驗結果，如衝擊條件以及螺栓之鬆緊等。因此，本研究將針對規範可能產生之實驗不確定性進行討論，提出修正型加速度輸入法理論，利用有限單元模型分析探討不確定因素對封裝元件之影響。在確認分析方法的正確性後，本研究針對晶圓級封裝進行結構設計及參數化分析，以增進封裝體在掉落測試的可靠度。
在掉落測試模擬分析部份，眾多學者採用的加速度輸入法（Input-G Method）之模擬方式，因其簡化方式省略許多影響因子，故無法探討上述之不確定因素。為解決上述之問題，本研究提出測試板掉落模型以及修正型加速度輸入法之有限單元模型進行模擬分析，並與實際掉落測試結果相互比對，以證明模型之可行性。在封裝元件之可靠度分析中首先針對封裝結構之受力行為進行討論，並探討實驗不確性因素、晶片厚度與大小、介電層之厚度與結構強度以及錫球之擺放方式對封裝結構之可靠度影響。
經測試板掉落模型以及修正型加速度輸入法之有限單元模型與實際掉落結果進行比對，研究結果指出此模擬方法具一定之可行性。在掉落測試之不確定性分析部份，研究結果指出螺栓鎖變鬆的條件下，因為測試板上下振盪幅度變大，使得晶片最外圍錫球承受較大之應力集中，本研究建議實驗時需時常檢查螺栓鬆緊度以提升實驗品質，避免不必要的誤差。在增強封裝元件之可靠度設計部份，適當減少晶片之厚度，有助於防止錫球承受過大之拉扯現象。採用較軟之介電層可提升該層對錫球之緩衝效果，故可有效吸收掉落撞擊所帶來之應力，若再增加介電層厚度可進一步提升錫球之可靠度。此外，晶片外圍擺放無訊號傳輸功能之錫球能有效分擔錫球受力情形，可提升封裝結構之可靠度。

關鍵字

晶圓級晶片尺寸封裝 ； 掉落試驗規範 ； 有限元素分析 ； 可靠度分析

並列摘要

Trends in electronic equipment development tend to focus on decreasing size, weight, as well as multiple functionalities. As a result, electronic handheld and portable devices, which are more prone to be dropping during their useful service life, are widely carried out with more capabilities and functions. Therefore, study of the dynamic response of electronic equipment and packages in reliability analysis has become increasingly important. The Board-level drop test method was proposed by the Joint Electron Device Engineering Council (JEDEC) to assess the drop performance of surface-mounted IC packages. However, in actual experiment, the uncertainties of drop conditions such as the impact pulse and screw conditions, etc, may cause the difficulties of repeatability of experiment, which may affect the reliability of the resulting packages. Therefore, the modified input-G method, which considered the screw binding force, was proposed in this research to discuss the uncertainty of drop conditions. After validating the method through an experiment, dynamic simulation of WLCSP structure was conducted using various design parameters to improve the reliability of the package.
The input-G method is widely used for conducting drop test dynamic analyses. Nonetheless, there are some limitations to the input-G method. The input-G method is unable to consider the uncertainty of the screw binding condition due to the simplicity of drop test equipment. Therefore, the free-drop model and the modified input-G method were proposed in this research. Moreover, experiment was also carried out to verify these methods. For the reliability analysis, this study focused on the mechanical behavior of the solder joints and investigated the effects of drop conditions and various design parameters, such as chip size, chip thickness, dielectric layer, and ball layout.
The results indicate that the simulation from free-drop model and the modified input-G method were close to the experiment data. It can thus be proven that these methods are reliable. In uncertainty analysis, the uncertainty of screw conditions consequently influences the dynamic behavior of the printed circuit board (PCB). Accordingly, the drop-induced stress in the solder joints was influenced by the tightness of the screw. The results reveal that for the WLCSP, the von Mises stress of the solder joint for loose screw binding condition is higher than tight screw binding condition because of less constraint at the PCB hole, the PCB board allowed a large deformation. Therefore, in an actual experiment, it is necessary to monitor screw tightness and re-tighten screws between drops to ensure the good repeatability of the experiment. In terms of design parameters, chip thickness reduction could also improve the package’s reliability due to less stretching occurring in the solder joint. The soft and thick dielectric layer can absorb the impact, thereby protecting the solder joint. Moreover, packages with enhancement balls can also share impact loading and help improve drop impact performance.

並列關鍵字

WLCSP ； JEDEC ； LS-DYNA ； Reliability Analysis

參考文獻

[3] JEDEC Solid State Technology Association, JESD22-B111：Board Level Drop Test Method of Component for Handheld Electronics Products, 2001.

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[5] S. T. Jenq., H. S. Sheu., C. L. Yeh., Y. S. Lai., J. D. Wu., “High-G drop Impact Response and Failure Analysis of a Chip Packaged Printed Circuit Board,” Journal of Impact Engineering, Vol.34, pp.1655-1667, March. 2007.

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