針對龐大數量內嵌式記憶體之測試技術開發與研究

現今的系統晶片 (System-on-Chip, SOC) 常大量使用數以百計，甚或上千個內嵌式記憶體作為資料儲存用途。為了提高資料傳輸頻寬，常選用高資料位元寬度的內嵌式記憶體規格。然而，針對如此龐大的記憶體數量，以及這種特殊的記憶體規格，在設計內建自我測試電路 (Built-in self-test, BIST) 時，將造成很高的繞線面積代價，進而提高了測試成本。過去已有許多研究學者針對上述問題提出解決方案。所提出的BIST電路採用序列式介面 (serial interface) ，例如使用IEEE 1500標準的序列式介面，來減少電路的繞線面積。然而，序列式的電路架構將導致測試時間的大幅拉長，且無法支援即時測試 (at-speed test) 的功能。在本論文中，我們提出了一個混合式 (hybrid) BIST架構，此種架構可以有效的降低BIST電路的繞線面積，同時可兼顧記憶體即時測試與診斷的需求。而其測試時間與傳統並列式(parallel) BIST架構相比只有極少量的增加。另一個影響測試成本的因素是測試機台。隨著製程技術的進步，量測內嵌式記憶體需要更昂貴的高階測試機台，這也意味著測試成本也將隨著製程技術的進步而水漲船高。為了降低測試機台的成本，許多不同領域的教授們以及學生們共同開發了后羿測試系統。后羿系統利用無線傳輸的方式以及改良的內嵌式測試電路，並配合測試流程的簡化以及增加測試平行度來達到大幅降低測試成本的目的。在本篇論文中，將先介紹后羿的概念、架構以及測試流程，再來將詳細地說明如何利用后羿測試系統實行內嵌式記憶體的測試與診斷的動作。實驗結果指出，針對業界0.18微米製程的實際例子，后羿測試系統確實可以達到大幅降低整體測試成本的目的。

關鍵字

內嵌式記憶體；自我測試；自我診斷；繞線面積；測試成本；后羿測試系統

並列摘要

It is common that an SOC contains hundreds or even thousands of heterogeneous embedded memories. Many of these embedded memories have wide data words, leading to a high routing penalty in the BIST circuits. Previous BIST schemes solve the problem by using a serial interface, e.g., a protocol based on the IEEE 1500 architecture or other scan approaches, to reduce routing area overhead. However, serial approaches are slow, and they do not allow at-speed test. In this thesis, we propose a hybrid BIST architecture that effectively reduces the routing penalty of BIST circuit, while allowing at-speed test and diagnosis of memory cores. The test time is close to that of a typical parallel BIST method. Another issue addressed here is that, embedded memory testing of advanced semiconductor products requires expensive Automatic Test Equipments (ATEs), and the cost becomes higher and higher as the manufacturing process technology keeps advancing. To address this issue, the HOY test system which features wireless communication and enhanced embedded test circuits has been developed. HOY reduces test costs dramatically, mainly due to the significant reduction in capital investment, simplification in test infrastructure and flow, increase in parallelism, etc. We first provide the concept, architecture, and test flow for future semiconductor products tested by HOY. We then discuss in detail the testing and diagnosis of embedded memories by HOY. A preliminary demonstration system also has been developed, and the experimental results show that the overall test cost for an industrial case based on 0.18-micron technology can be greatly reduced.

並列關鍵字

Embedded memory ； Built-in self-test ； Built-in self-diagnosis ； Routing area ； Test cost ； HOY test system

參考文獻

[41] T.-W. Ko, Y.-T. Hsing, C.-W. Wu, and C.-T. Huang,

[1] Semiconductor Industry Association, “International

technology roadmap for semiconductors (ITRS), 2007

Proc. Tenth IEEE Asian Test Symp. (ATS), Kyoto, Nov.

National Tsing Hua University, Hsinchu, Taiwan, June

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針對龐大數量內嵌式記憶體之測試技術開發與研究

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