- 學位論文
適用於里德-索羅門碼建構之低密度奇偶檢查碼之多模解碼器架構
A multi-mode decoder architecture for RS-LDPC codes
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摘要
一個好的低密度奇偶檢查碼解碼器通常須具備以下的功能：好的位元錯誤比率、高資料傳輸率以及提供多種模式。對於目前各種現有的低密度奇偶檢查碼解碼器而言，幾乎無法同時達到這三種需求。而在本篇論文中，我們以里德-索羅門碼建構之低密度奇偶檢查碼為例，實作出可達到此三種需求之解碼器。對於一個有效率的多模式的低密度奇偶檢查碼解碼器而言，大部分的硬體資源如排列器應該要在不同模式間共用。雖然里德-索羅門碼建構之低密度奇偶檢查碼並不是準循環模式，但在本篇論文中，我們發現在其同位元檢查矩陣架構中所隱含的架構規則，非常適合用來設計有組態的排列器。採用部分平行化的架構連同我們所提出的排列器，可降低因為多模式所引起的實作複雜度。對於高比例的低密度奇偶檢查碼而言，其高檢查節點維度導致高資料傳輸率的解碼器實作上的困難。為了克服這項困難，我們將同位元檢查矩陣的變數節點分成好幾個群組，依序處理每個群組降低主要路徑的延遲，進而增加傳輸率。為了更進一步增加傳輸率，使用修改過的縱向混合解碼演算法可以有效地增加收斂速度，並且在達到既定的位元錯誤比例下降低解碼迴圈數。我們使用90nm CMOS製程實作了兩個可以提供多種模式的解碼器，且可以達到每秒10的六次方個位元數的資料傳輸率。
並列摘要
For an efficient multi-mode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi cyclic, in this thesis, we re-veal that the structural properties inherent in its parity-check matrix can be adopted in the design of congurable permutators. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the throughput. To further increase the throughput, shuffled message-passing decoding is adopted to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance. Using a 90-nm CMOS process, multi-mode decoders that can achieve multi-Gbit/s throughput have been implemented.
參考文獻
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