應用類神經網路建構晶圓圖故障圖樣辨識模式

Development of Wafer Bin Map Pattern Recognition Model - Using Neural Network Approach

魏連均(Lian-Jun Wei)

指導教授 ： 陳飛龍

國立清華大學/工學院/工業工程與工程管理學系/碩士(2006年)

摘要

近年來半導體製造技術的複雜程度迅速倍增，製造過程往往包含二、三百道的製造程序，製程中許多製程參數均被自動地記錄於工程資料庫內，以供工程師隨時調閱。然而面對這些龐大且複雜的工程資料，工程師不容易迅速地察覺出可能導致異常的原因，因此如何將大量的工程資料經過有效的分析處理，轉換成有價值的資訊或知識，並且將其儲存回資料庫中，作為以後工程師解決相關問題的參考依據，則成為半導體廠之良率管理與提升的重要議題。
當產品發生低良率的問題時，晶圓圖能提供追查產品發生異常原因的重要線索，不同的事故原因可能會在晶圓圖上形成不同的故障圖樣，因此利用晶圓圖來追溯異常原因應可以達到很好的效果。目前半導體廠對於晶圓圖故障圖樣的辨識，大部分仍採用人工辨識的方式進行，但是由於人員疲勞與人為主觀因素的影響，常造成圖樣分類結果的不一致。因此，本研究提出二階段晶圓圖故障圖樣辨識系統，第一階段將轉換後的晶圓圖故障圖像透過空間圖樣分析來過濾出系統性故障圖樣，之後擷取出具代表性之特徵值，作為第二階段類神經網路之輸入資料，透過監督式學習之倒傳遞網路與學習像量量化網路的比較，選擇出較佳的網路模式來辨識晶圓圖之中心聚集、邊緣失效、區域性、環狀、直線型故障圖樣。
在本研究中收集了某一半導體廠實際的晶圓圖相關資料，並建立系統以驗證辨識模式之成效，而實證分析結果顯示，系統之第一階段能過濾出最終之系統性故障圖樣，爾後所擷取出之特徵值確實可以解決以往相關研究中故障圖樣大小及方向性的問題，並透過第二階段之類神經網路模式可以正確辨識出晶圓圖故障圖樣。

關鍵字

半導體 ； 類神經網路 ； 晶圓圖

並列摘要

In semiconductor manufacturing, the manufacturing parameters are recorded automatically to provide information to engineers. But it is hard to find out the root cause of the problem from the enormous database. The engineers cannot response quickly when problems occur. To build up the knowledge database by analyzing and transforming data into useful information has become the vital issues of yield management and improvement in semiconductor factory. The bin-map can provide clues to identify the cause when low-yield situation happens. We can trace to specific root cause depending on the different pattern types of bin-map. Nowadays, the recognition of bin-map is performed manually. The individual fatigue and emotion will affect the results of pattern recognition. Therefore, this research intends to develop a two-phase bin-map pattern recognition system. The first phase is using the bin-map pattern to get the wafers with systematic failed patterns via Spatial Signature Analysis. At the same time, the features extracted form systematic failed patterns serve as the inputs for constructing the neural network in the second phase. This research selects the better model from two trained models i.e., LVQ model, of neural network to recognize the center type, edge type, local type, ring type and line type.
The developed methodology is verified with industrial data from a famous semiconductor company. The existing neural-network approaches for recognizing the bin-map patterns on the wafer are limited by the size and the orientation of bin-map patterns. The experimental results demonstrate that the proposed methodology can not only solve this problem by extracting features, but also effectively identify the bin-map patterns on the wafer.

並列關鍵字

Semiconductor ； Neural Network ； Wafer Bin Maps

參考文獻

Breaux, L. and Singh, B., “Automatic defect classification system for patterned semiconductor wafers,” IEEE/UCS/SEMI International Symposium on Semiconductor Manufacturing, pp. 68-73, 1995.

Chen, F. L. and Liu, S.F., “A neural-network approach to recognize defect spatial pattern in semiconductor manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 3, pp. 366-373, 2000.

Chen, F. L. and Lin, S. C., “Logic product yield analysis by wafer bin map pattern recognition supervised neural network,” IEEE Transactions on Semiconductor Manufacturing, pp. 501-504, Oct. 2003.

Chien, C. F., Lin, T. H. and Liu, Q. W., “Developing A Data Mining Method for Wafer Binmap Clustering and An Empirical Study in A Semiconductor Manufacturing FAB,” Journal of the Chinese Institute of Industrial Engineers, Vol. 19, No. 2, 2002.

Cunningham, S. P., Spanos, C. J. and Voros, K., “Semiconductor Yield Improvement: Results and Best Practices,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 2, pp. 103-109, 1995.