並列摘要
Factoring is a technique of logic minimization to represent a Boolean function in a equivalent function with minimum literals. When realizing the circuit, a function represented in compact form has minimum area. Some Boolean functions even have equivalent forms which each variable appears exactly once in factored functions, which are known as fanout-free functions. John P. Hayes had devised an algorithm to recognize fanout-free functions. We propose a property and some e±cient ways to accelerate this algorithm. With our improvements, execution time of this algorithm are more competitive with other state-of-the-art methods.
參考文獻
[1] H Allen Curtis, "A New Approach to the Design of Switching Circuits", Van Nostrand, Princeton, 1962.
[2] John P. Hayes, "The Fanout Structure of Switching Functions", Journal of the ACM, 22:551-571, 1975.
[3] Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, and Alberto L. Sangiovanni-Vincentelli, "Logic Minimization Algorithms for VLSI Synthesis", Kluwer Academic Publishers, 1984.
[4] Kurt Keutzer, "DAGON: Technology Mapping and Local Optimization", Proceedings of the 24th Design Automation Conference (DAC'1987), pp. 341-347, 1987.
[8] Shin-Ichi Minato and Giovanni De Micheli, "Finding All Simple Disjunctive Decompositions Using Irredundant Sum-of-Products Forms", Proceedings of the 1998 IEEE/ACM International Conference on Computer-aided Design (ICCAD'1998), pp.111-117, 1998.