一個針對H.264/MPEG-4高解析度影像的有效率畫面預測器架構設計

An Area-Efficient Intra Predictor for High Resolution H.264/MPEG-4 AVC Decoding

張元鴻(Yung-Hung Chang)

指導教授 ： 林永隆

國立清華大學/電機資訊學院/資訊工程學系/碩士(2006年)

https://doi.org/10.6843/NTHU.2006.00298

摘要

我們在此論文中提出一個針對H.264/MPEG-4高解析度影像的有效率畫面預測器架構設計。在H.264/MPEG-4標準中定義了17種預測模式，然而在解碼端對於亮度像素我們只根據其中的一種預測模式來做運算；對於彩度像素我們根據另一種預測模式來做運算。因此有效率的使用硬體資源是實作出低成本電路的關鍵所在。我們提出了新穎的資料選擇及有效率重複使用的機制來完成我們的畫面預測器。我們的設計在成本上是非常經濟的(18.8K gates)。而且它只需要127個時間單位(每個時間單位是10-8秒)來預測一個包含384個像素的區塊。在這樣的運算速度下，我們的設計可以在一秒鐘內及時的預測出30張3680 x 1536的影像。它也通過了功能及時序上的驗證。最後我們將這個畫面預測器整合進一個H.264解碼系統，並放到系統單晶片多媒體平台上去驗證。這個H.264解碼系統能成功的在這個系統單晶片多媒體平台上即時的播放影像。

關鍵字

畫面預測器

並列摘要

We propose an area-efficient architecture for intra prediction in H.264/MPEG-4 AVC video decoding. There are 17 possible prediction modes defining how each pixel is predicted. However, in the encoded bitstream only one mode is used to predict luma component and another for chroma component. Therefore, resource sharing is the key to efficient implementation of hardwired intra predictor for low cost and high resolution applications. We propose a novel data routing and reuse scheme to implement our intra predictor. It takes only 127 cycles to predict a macroblock. Our design is economical (18.8K gates) and high performance (100MHz @ TSMC 0.13μm). It can support real-time decoding of 3680 x 1536 @ 30 fps. Our design has passed both cell-based and FPGA-based gate-level simulation for a large set of test video sequences and has been successfully integrated into a hardwired main profile decoder on a multimedia SOC platform.

並列關鍵字

intra predict

參考文獻

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