薄膜電晶體特性與可靠度分析

Characteristics and Reliability of Thin Flm Transistors

鄭志宏(Chi-Hong Cheng)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/碩士(2006年)

https://doi.org/10.6843/NTHU.2006.00382

摘要

在這本論文裡，我們設計並且製造了多種結構的多晶矽薄膜電晶體。實驗結果顯示出具有多通道及多閘極的薄膜電晶體會有較好的初始特性，諸如較高的導通電流、較低的臨界電壓及較小的次臨界斜率。這是由於多通道的薄膜電晶體可以增加閘極對於通道的控制能力並且得到好的初始特性。而多通道薄膜電晶體的漏電流相對於單一通道的元件也減少許多，這是由於有更多的矽-氮鍵可以形成因而減少漏電流。而多閘極薄膜晶體初始特性的改善也被觀察到，例如較高的導通電流、較低的臨界電壓及較小的次臨界斜率。然而在熱載子應力測試後，多通道及多閘極的薄膜電晶體都有較多的衰退特性，輕摻雜汲極(LDD)或是閘極重疊輕摻雜汲極(GOLDD)設計可以用來抑制嚴重的離子轟擊並且改善特性。
電漿蝕刻對於薄膜電晶體的影響也在本論文中被探討。實驗結果顯示面積效應及周長效應對於薄膜電晶體在元件初始特性上均沒有明顯的影響。而在熱載子應力測試後，元件特性均隨著時間的增加而衰退許多。對於面積效應薄膜電晶體而言，電漿蝕刻產生的傷害和閘極面積比例沒有明顯關係；而對於周長效應薄膜電晶體，電漿蝕刻所造成的傷害是更為顯著的。這是由於元件具有較大的周長相對於較小的周長會收集較多的電荷。電漿蝕刻效應對元件造成潛在的傷害諸如固定氧化層缺陷(Oxide trap charges)並且產生較多的介面陷阱(Interface trap charges)。增加氧化層的強度是被認為可以減少電漿蝕刻傷害的方法之一。

關鍵字

薄膜電晶體 ； 電漿蝕刻 ； 可靠度

並列摘要

In this thesis, we designed and fabricated poly-Si TFTs with various design structures. Experiment results reveal that TFTs with multi-channel design can obtain better initial characteristics such as higher Ion current, lower threshold voltage, and smaller subthreshold swing. It is because that multi-channel structure can enhance gate control ability, and furthermore improve initial characteristics. Also the leakage current of TFT with multi-channel is eliminated compared with single channel due to more effective region passivation can performed. As for multi-gate TFTs, the improvement on initial characteristic is also observed. And multi-gate TFT exhibits higher Ion current, smaller threshold voltage, and smaller subthreshold swing. After hot carrier stress, TFTs with multi-channel and multi-gate design both show poor reliability than that with single gate one which may due to higher Ion impact ionization. LDD or GOLD design can be adopted to suppress severe impact ionization induced reliability instability.
Then TFTs with plasma charging effects were investigated. The initial characteristics of area antenna and peripheral antenna show less dependence to plasma charging effect. After hot carrier stress, parameter degradation and variation change with stress time. TFTs with higher area ratio (AR) don’t show obvious reliability degradation by plasma charging damage. As for peripheral TFTs, the plasma charging induced damage become vivid. It is concluded that TFTs with larger peripheral length can collect more charges than shorter peripheral one. The plasma charging damage may induce more fixed oxide trap charges and contribute poorer interface such as more interface trap states. Strengthening the roughness of the gate dielectric is one of the strategies for reducing the damage induced by the plasma charging damage effects.

並列關鍵字

Thin Film Transistors ； Plasma ； relaibility

參考文獻

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