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  • 學位論文

VCO及高速OOK調變的發送機設計

Design of VCO and High Data Rate Transmitter with OOK Modulation

指導教授 : 徐碩鴻

摘要


隨著資訊快速發展,可用頻寬逐漸成為資料傳輸的一大考量。為了追求更高的傳輸速率、更多的可用頻段,遂逐漸把電路操作的頻率往更高頻推動。然而高頻運作底下,更多的挑戰及困難是電路設計者必須去思考的問題。 在本篇論文中提出了兩組V頻帶的VCO。首先對電感電容的組合電路做一系列分析,並以此為基礎設計第一組電路,提出一組可變電感,是利用可變電容及其寄生電感組合而成,以之改善高頻運作時可變電容品質因數不佳的問題。當操作頻率高於可變電容的自振頻之後,可變電容所呈現的電抗會從電容性轉變成電感性,且等效到tank的loss會變小。模擬結果顯示此VCO在消耗50 mW的情形下,可運作於61 GHz,相位雜訊在1MHz處則為-98.8 dBc/Hz。在第二組電路的設計中,提出一組共振輸出緩衝級來防止50 ohm的負載對核心振盪電路的影響。在VDD=1.2 V消耗直流11.2 mA的情形,量測結果顯示輸出中心頻率為55 GHz,相位雜訊在1 MHz處為-91.3 dBc/Hz,調頻範圍1.3 GHz,DC轉RF的功率效益達2.8%,FOM=-174.9。 接著提出兩組應用於有線傳輸的高速OOK調變發送機。在高頻電路參考文獻有許多採用ASK(OOK)的方式,然而傳統ASK(OOK)電路架構在高頻時衰減嚴重,若加大ASK尺寸來提升功率則會面臨開關切換速度變慢,以及on/off隔離能力較差。在本論文中分別提出載波為20-GHz及60-GHz兩組不同架構的OOK發送機。20-GHz的OOK發送機採用觸發、調變、輸出緩衝三部分組成,此架構改善傳統ASK(OOK)的on/off的訊號差,增快資料傳輸速率。量測結果顯示在0.18 um CMOS製程下可達到4 Gb/s的調變速率。另一組60-GHz的OOK發送機,考量到傳統OOK動輒全開全關,會導致VDD的浮動,進而影響其他電路的運作。這邊利用特殊的電路架構實現OOK調變,可保持電路在on跟off的切換不會造成太大的電流改變,提升電路的穩定性。量測結果顯示電路在data rate達3.5G bps時皆有正常調變,此電路面積為0.18mm2,耗能為8.3 pJ/bit。

並列摘要


With the rapid development of information technology, the bandwidth requirement for data transmission becomes a major concern. The operating frequency of circuits is pushed towards microwave frequency range to pursue a higher data rate and more available spectrums. However, there are also more challenges and difficulties for IC designers at high frequencies. In this thesis, two voltage-controlled oscillators operating at V-bands are proposed. The fundamental analysis of different LC combinations is discussed first. In the first design, an variable inductor implemented by the parasitic inductor of a varactor is used to solve the problem of poor quality factor the varactor at high frequencies. When the operating frequency becomes higher than the self-resonance frequency of the varactor, the reactance will transfer the capacitance to inductance, and the loss to the tank will become smaller. The simulated results show that the VCO is capable of operating at 61GHz with a phase noise of -98.8 dBc/Hz, under a power consumption of 50mW. In the second design, a resonant output buffer configuration is proposed to prevent the degradation of VCO core circuits under 50 ohm condition at high frequencies. Under VDD of 1.2V with DC current about 11.2mA, measurement results demonstrate that the VCO has an center frequency at ? GHz, phase noise at 1MHz offset of -91.3 dBc/Hz, a tuning range of 1.3GHz, and the efficiency of DC to RF power is 2.8% with an FOM=-174.9. Following the VCO design, two high speed OOK transmitters for wireline communications are proposed. One critical problem of using conventional ASK (OOK) modulation in these transmitters is serious attenuation at high frequencies. If increasing the transistor size to enhance the power, the obvious tradeoffs are a lowered switching speed and degraded on/off isolation. In this thesis, we propose two different OOK-based transmitters operating at the carrier frequencies of 20 and 60 GHz, respectively. The 20-GHz OOK transmitter consists of three parts including the trigger, modulator, and the output buffer. With the proposed topology, the isolation between the on and off states is improved, and the speed of data transmission is increased. The measurement results show that the modulating rate up to 4G bps at 0.18um CMOS process. In addition, the design of a 60-GHz transmitter takes into consideration of the problem in a traditional OOK design, where the full signal swing can lead to VDD disturbance, affecting the operation of other circuits. A different circuit topology is proposed here to achieve the OOK modulation, which can reduce the impact during the on/off state change and improve the circuit stability. Measurement results show that the modulation is correct as the data rate increases up to 3.5G bps. The circuit core area is 0.18mm2 and the energy consumption is 8.3pJ/bit.

並列關鍵字

VCO OOK varactor transmitter

參考文獻


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