三角積分鎖相迴路量化雜訊抑制相關技術

Quantization Noise Suppression Techniques in Delta-Sigma Phase-Locked Loops

劉熙恩(Hsi-En Liu)

指導教授 ： 張慶元 ； 黃錫瑜

國立清華大學/電機資訊學院/電機工程學系/碩士(2013年)

摘要

鎖相迴路已經是目前不可或缺的重要時脈產生器來源，尤其是在無線通訊收發器中，鎖相迴路被用來當作頻率合成器，合成出不同的頻率時脈與所接受到的高頻信號相乘，進而降頻至基頻進行信號處理，為了因應頻道間距以及通訊品質，頻率合成器的頻率解析度和相位雜訊是時脈設計很重要的考量因素。
　　由於典型的整數型鎖相迴路頻率解析度受限於參考時脈，因此頻率合成器必須使用三角積分鎖相迴路來完成，但其平均的概念伴隨著量化雜訊，許多技術發展出來抑制這些雜訊，其中提高三角積分器的超採樣率，將量化雜訊移至更高頻率被濾波的方法是本論文主要採用的技術。
　　有別於已發表的高超採樣率三角積分鎖相迴路，本論文首先分析除頻器與頻率偵測器之間的離散與連續時間轉換介面，並且為此介面的行為設計了因應的數位有限脈衝響應濾波器在三角積分器的輸出，並且搭配所提出的半整數除頻器，以抑制量化雜訊，並且在特定頻率有更進一步的濾波效果，相較於傳統的三階三角積分鎖相迴路的量化雜訊有21 dB的抑制量。
　　晶片是使用台積電 180 nm CMOS 混合信號製程所設計，頻率合成器頻率範圍為 2.58 GHz 到 3.45 GHz ，核心電路功率消耗約為 12 mW ，量測時搭配 FPGA 板來實現三角積分調變器以及有限脈衝響應濾波器，量測結果驗證了在 1/5 及 3/5 倍參考頻率處有更進一步的濾波效果。

關鍵字

鎖相迴路 ； 三角積分 ； 量化雜訊抑制 ； 高超採樣率三角積分鎖相迴路 ； 半整數除頻器

並列摘要

In modern wireless communication systems, frequency synthesizers with high frequency resolution are used to up/downconvert signals to desired bands precisely. Phase-locked loops (PLLs) with the delta-sigma technique are a common way to achieve high frequency resolution. However, quantization noise is inevitable introduced during division ratio dithering, it greatly degrades the out-band noise performance especially in a high-bandwidth phase-locked loop.
We focus on the study of quantization noise suppression. Analysis of quantization noise from delta-sigma modulation and the interface between continuous-time and discrete-time signal processing in PLLs plays an important role in this thesis. Based on this analysis, we propose a high oversampling rate (H-OSR) delta-sigma frequency synthesizer on which an finite-impulse response (FIR) digital filter and a novel half-integer frequency based on the phase compensation technique are embedded.
The simulation result shows that the proposed architecture is able to suppress the quantization noise by 21 dB compared with the conventional MASH 1-1-1 structure. Moreover, the notch filtering effect from the FIR filter can further reduce quantization noise at the specific frequency, and improve the phase jitter performance.
The proposed frequency synthesizer was verified by the silicon results in a TSMC 0.18μm CMOS process. Output frequency range is from 2.58 GHz to 3.45 GHz, the core power consumption is 12 mW. At the frequency of 1/5 and 3/5 reference frequency in the phase noise spectrum, the notch filtering effect can be found. Besides, FPGA is used to implement the delta-sigma modulator and the FIR filter during the measurement.

參考文獻

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