應用於語音訊號的低功耗連續時間三角積分調變器利用數值最佳化設計方法

Power-Efficient CT ΣΔ Audio Modulator Design Using Numerical Optimization Methodology

陳韋霖(Wei-Lin Chen)

指導教授 ： 謝志成

國立清華大學/電機資訊學院/電機工程學系/博士(2013年)

https://doi.org/10.6843/NTHU.2013.00075

摘要

本論文提出了一個將連續時間三角積分調變器轉成離散模型的方法並可以在此離散模型中考慮各種非理想效應。我們推導出一個遞迴關係式用來得到連續時間迴路濾波器的等效離散轉換函數，而此連續時間迴路濾波器可包含著各種非理想效應，例如放大器的有限增益、有限頻寬、額外迴路延遲等等。而這樣的模型可以讓這些非理想效應在系統合成中就可以考慮進來。我們的方法統合了目前有關將連續時間三角積分調變器轉為離散模型的方法並且可以應用在各種階數的迴路濾波器以及各種數位類比轉換器的輸出波型。根據此離散模型，我們利用數值最佳化方法來進行迴路濾波器的係數調整可以得到一個三階低通連續時間三角積分調變器的非理想效應被大幅度降低。
根據上述的方法，我們設計了一個應用於語音訊號的低電壓、低功耗三階連續時間三角積分調變器。為了操作在低電壓，此調變器使用了輸入前饋的架構搭配上一個1.5位元的量化器來降低迴路濾波器的內部訊號大小。我們利用了數值最佳化的方法來合成迴路濾波器的係數，藉此最小化頻段內的量化雜訊並且降低了放大器的規格要求以及功率消耗。為了操作在0.5伏以下的操作電壓，我們發展出了一個偽差動、反向器架構的運算放大器以及本體推動的共模迴授電路。量化器則是採用本體推動、多端輸入的regenerative latch來達成前饋係數和相加的功能。此調變器利用90-nm CMOS製程，在20-kHz的訊號頻寬內達到80.2-dB的最高動態範圍以及77.1-dB的最高SNDR。此調變器的晶片面積為0.14-mm2並且在450-mV操作下消耗了9.1-μW。FoM為39-fJ/conv-step，和其他的成果比較相當具有競爭力。

關鍵字

連續時間 ； 額外迴路延遲 ； 三角積分調變 ； 類比數位傳換 ； 低功耗 ； 低電壓

並列摘要

This thesis proposes a method for the discretization of continuous-time sigma-delta modulators (CT-ΣΔMs) with various circuit nonidealities. Recurrence equations for the sampled states of a CT-ΣΔM are derived to find the equivalent discrete-time (DT) transfer functions of CT loop filters along with several second-order effects, such as finite DC gain, finite unity-gain bandwidth (GBW) of an amplifier, and excess loop delay (ELD), etc. This allows a synthesis flow that considers these nonidealities at the system level. The proposed approach generalizes existing works relating to the DT modeling of a CT-ΣΔM, and is applicable to arbitrary-order loop filters with unconstrained digital-to-analog converter (DAC) output waveforms. According to the DT model, a third-order low-pass modulator design based on a numerical optimization shows that the second-order effects of a CT-ΣΔM can be noticeably mitigated by the appropriate coefficient scaling.
Based on this methodology, a low-voltage low-power third-order continuous-time sigma-delta modulator for audio applications is designed. For low-voltage operation, the modulator employs an input-signal-feedforward architecture and a 1.5-bit quantizer to reduce the internal signal swings in a loop filter. The loop filter coefficients are synthesized based on a numerical optimization to minimize in-band quantization noise power, noticeably relaxing op-amp requirements and saving power consumption. For operating from a sub-0.5-V supply voltage, a pseudo-differential inverter-based single-stage op-amp incorporating a bulk-driven common-mode feedback (CMFB) circuit is developed. The quantizer is implemented with a bulk-driven multi-input regenerative latch to perform the feedforward coefficients and summing. The prototype modulator is fabricated in 90-nm CMOS technology, achieving an 80.2-dB peak dynamic range and a 77.1-dB peak SNDR over a 20-kHz bandwidth. The modulator occupies core area of 0.14-mm2 and dissipates only 9.1-μW from a 450-mV power supply. The figure of merit (FoM) of overall modulator is 39-fJ/conv-step, which is competitive to state-of-the-art designs.

並列關鍵字

Continuous-time ； Excess loop delay ； Sigma-delta modulation ； Analog-to-digital conversion ； Low-power ； Low-voltage

參考文獻

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