使用氧化鉿及氧化鈰薄膜之電容器與場效電晶體的電性與可靠性分析

The Electrical and Reliability Properties of Metal-Insulator-Silicon Capacitors and Field-effect Transistors with HfO2 and CeO2 Gate Dielectris

陳俊衡(Chun-Heng Chen)

指導教授 ： 李雅明

國立清華大學/電機資訊學院/電子工程研究所/碩士(2007年)

https://doi.org/10.6843/NTHU.2007.00205

摘要

本實驗成功的製作了金屬(Al)/氧化鉿(HfO2)/半導體(p-Si)與金屬(Al)/氧化鈰(CeO2)/半導體(p-Si)兩種結構的電容器、n 通道場效電晶體。探討在不同型態電流應力下崩潰電荷的可靠度特性，同時利用閘控二極體的技術探討使用氧化鈰與氧化鉿/氧化鈰堆疊結構為閘極絕緣層的介面特性。針對9.12 nm, 8.2 nm與6.51 nm不同厚度下的氧化鉿薄膜，施加定電流應力，分別萃取出的韋布斜率為3.42, 2.90與1.83。針對不同的指數0.6與1，可以藉由細胞基礎分析模型得到氧化鉿薄膜的缺陷密度分別為0.97nm與1.63nm。針對厚度為9.12 nm的氧化鉿薄膜，使用傳輸線脈衝波應力測試，得到的韋布斜率約為3.86。使用傳輸線脈衝波應力所得到的崩潰電荷值比起由定電流應力下得到的約小上5個數量級。然而，我們利用電洞產生係數分析發現，傳輸線脈衝波應力下的係數比起定電流應力下的約大上4個數量級。因此我們可以定量的解釋兩種應力下崩潰電荷值的差距。
使用次臨界斜率萃取得氧化鈰與氧化鉿/氧化鈰堆疊結構為閘極絕緣層的介面缺陷密度分別為1.47×1012 cm-2 eV-1和1.53×1012 cm-2 eV-1。藉由閘控二極體與次臨界斜率得到氧化鈰與氧化鉿/氧化鈰堆疊結構在高介電薄膜與矽基板處的等效捕陷截面積分別為8.68×10-15 cm2 和4.83×10-15 cm2。

關鍵字

高介電常數薄膜 ； 氧化鉿 ； 氧化鈰 ； 崩潰電荷 ； 缺陷密度 ； 閘控二極體 ； 介面捕陷密度 ； 等效捕陷截面積

並列摘要

Metal-insulator-semiconductor (MIS) capacitors and n-channel field effect transistors with HfO2 and CeO2 gate dielectrics were successfully fabricated. The reliability properties such as charge-to-breakdown (QBD) with different types of current stress were characterized. The high-k/Si interface properties with CeO2 and HfO2/CeO2 laminated gate oxides were investigated by the gated-diode technique. The Weibull slope and the defect size of HfO2 gate dielectric were determined. The extracted Weibull slope (β) from constant current stress (CCS) measurement for different thicknesses of 9.12 nm, 8.2 nm and 6.51 nm are found to be 3.42, 2.90 and 1.83, respectively. The defect size a0 extracted by the cell-based analytic model with different exponents of 0.6 and 1 are 0.97 nm and 1.63 nm, respectively. The extracted Weibull slope (β) from transmission line pulsing (TLP) measurement for thickness of 9.12 nm is about 3.86. The QBD values extracted from the TLP method are about 5 order of magnitude smaller than those extracted from the CCS method. However, the hole generation coefficient extracted from the TLP method is about 4 order of magnitude larger than that extracted from the CCS method. Hence, this can quantitatively explain the difference of QBD between the CCS method and the TLP method.
The interface trap density (D¬it) of CeO2 and HfO2/CeO2 laminated gate dielectrics determined by the subthreshold swing method are 1.47×1012 cm-2 eV-1 and 1.53×1012 cm-2 eV-1, respectively. The effective capture cross section of surface state (σs) of CeO2 and HfO2/CeO2 laminated gate oxides extracted using the gated diode technique and the subthreshold swing measurement were about 8.68×10-15 cm2 and 4.83×10-15 cm2, respectively.

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