應用於高速網路交換機之1:16/20 解串列多工器

Quarter-Rate 1:16/20 Demultiplexer for High Speed Switch Fabric Application

盧明豪(Ming-Hao Lu)

指導教授 ： 許雅三

國立清華大學/電機資訊學院/電機工程學系/碩士(2007年)

摘要

隨著光纖通訊和網路技術的發展，資料傳輸所要求的速度也隨之增加，因此應用於高速傳輸之I/O介面的設計也就變得十分重要。幾近年來，串列傳輸的技術愈來愈廣泛地被應用在高速資料傳輸通訊之上。在串列傳輸的技術中，串列及解串列器(SerDes)是一個相當重要的電路。串列多工器能將低速的平行資料匯流排(parallel data bus)轉換為一道高速的串列資料流(serial data stream)並傳送出去，相反的，解串列多工器則是將接收進來的高速資料流解成低速的平行資料匯流排。藉著使用串列及解串列器介面，我們能夠輕易地提升整體電路的頻寬而不會增加過多的針腳數。系統的可擴充性也能夠獲得改善。因此，我們將這樣的串列及解串列器介面應用於負載平衡Birkhoff-van Neumann交換機晶片的設計，以建構一個高速的網路交換機系統。
在本篇論文中，我們將著重於一個四分之一時脈頻率(quarter-rate)的1:16/20解串列多工器的設計及實作上。在這個設計中，我們提出了一個新的quarter-rate電路架構來實現這個1:16/20雙模的解串列多工器電路，quarter-rate的電路架構能夠減輕高頻時脈訊號的負載，並且在quarter-rate時脈之下，電路能夠更加穩定的操作。我們提出的quarter-rate電路架構是結合了樹狀架構(binary tree type architecture)和多相位時脈取樣架構(multiple-phase sampling architecture)來達到非二冪次的解串列功能，為了高速操作的考量，在這個1:16/20解串列多工器的設計之中我們使用了CML及TSPC的電路設計技巧。我們使用台積電的0.18μm和0.13μm CMOS的製程將這個quarter-rate 1:16/20解串列多工器實作出來。在0.18μm的解串列多工器設計中，所有的電路都是使用RF的元件以增進電路在高頻操作的效能。我們將quarter-rate 1:16/20解串列多工器整合在單一channel SerDes介面的晶片之中，整個SerDes電路的面積為2.49mm × 2.49mm，在晶片量測上，這個SerDes晶片可以達到5.12Gbps的資料傳輸速度。
而在0.13μm的解串列多工器設計中，我們是使用相同的quarter-rate架構來實作1:16/20解串列多工器，但在設計有做了一些改變。在1:16/20解串列多工器的實作上，我們混合使用了RF和baseband的元件來減少面積的耗費。藉由這個方式，0.13μm的解串列多工器電路的面積可以縮小到只有0.18μm解串列多工器的30%。我們將0.13μm的解串列多工器電路整合在一個4 × 4的負載平衡交換機晶片之中。這個4 × 4的負載平衡交換機晶片包含了數位的交換機核心電路部分以及quad SerDes介面，在quad SerDes的時脈訊號傳輸上使用了GCPW傳輸線，以減小不同channel之間時脈訊號的偏差，整個交換機晶片總面積為3mm × 2.48mm。我們已經驗證了每一個SerDes介面可以達到7Gbps的速度。由此我們可以估測這個4 × 4的負載平衡交換機晶片可達到總吞吐為28Gbps.

關鍵字

解串列多工器 ； 串列解串列器 ； 多相位取樣架構 ； 負載平衡式交換機晶片

並列摘要

As the optical communication and network technology improve, the required transmission data rate also increase gigabit-per-second range. High speed I/O interface design becomes an important issue. In the recent year, serial link transmission method is extensively used in high speed communication. The serializer/deserializer (SerDes) interface plays an important in serial link transmission. The multiplexer converts the low-speed parallel data bus into a high-speed serial data stream and transmits the serial data stream out. On the contrary, the demultiplexer receives the high-speed data stream and converts the data stream into low-speed data bus. By using the SerDes interface, we can easily increase the overall circuit bandwidth without increasing the pin count. The system scalability is also improved. We employ the SerDes interface in the load-balanced Birkhoff-van Neumann switch fabric design to build up a high speed network switching system.
In this thesis, we focus on the design and implementation of the quarter-rate 1:16/20 demultiplexer. We propose new quarter-rate architecture to realize the 1:16/20 dual-mode demultiplexer. The quarter-rate architecture relaxes the loading of the high frequency clock signal and the circuit operating at quarter-rate speed would work more stable. The quarter-rate architecture combines the binary tree type and multiple-phase sampling architecture to achieve the non-power-of-two demultiplexer function. The CML and TSPC circuits are employed in the 1:16/20 demultiplexer design for high speed consideration. The quarter-rate 1:16/20 demultiplexer design is realized in TSMC 0.18μm and 0.13μm CMOS technology. In 0.18μm demultiplexer design, the whole circuits are implemented by the RF model device to improve high frequency operation performance. We integrate the 1:16/20 demultiplexer in the one-channel SerDes interface. The total area of the SerDes is 2.49mm × 2.49mm. In the chip measurement, the one-channel SerDes interface can work up to 5.12Gbps data rate.
In 0.13μm demultiplexer, we use the same architecture to implement the 1:16/20 demultiplexer but do several changes. We mix the RF and baseband model device in the 1:16/20 demultiplexer implementation and the circuit area can be reduced. The area consumption of the 0.13μm demultiplexer is only 30% of the 0.18μm design. The 1:16/20 demultiplexer is integrated in the 4 × 4 load-balanced switch fabric. The 4 × 4 load-balanced switch fabric consists of the digital switch core circuit and quad SerDes interface. The grounded coplanar waveguide (GCPW) type transmission line is employed to reduce the clock tree skew for the quad SerDes to within 1ps. The total area of the 4 × 4 load-balanced switch fabric circuit is 3mm × 2.48mm. We have verified that each SerDes interface can work up to 7Gbps in the quad SerDes interface. Therefore, we can estimate that the maximum throughput of the 4 × 4 switch fabric is about 28Gbps.

並列關鍵字

Demultiplexer ； SerDes ； Multiple-phase sampling architecture ； Load-balanced switch fabric

參考文獻

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