針對多媒體嵌入式數位訊號處理器基於硬體特殊最佳化之超長指令集後處理編譯器框架

A VILW-Based Post Compilation Framework for Multimedia Embedded DSPs with Hardware Specific Optimizations

鄭孟璿(Meng Zheng)

指導教授 ： 鍾葉青

國立清華大學/電機資訊學院/資訊工程學系/碩士(2007年)

摘要

在高性能和低功耗多媒體嵌入式系統設計中，由於超長指令集的嵌入式觸位訊號處理器需要編譯器來進行排程來增加指令層次平行所以變得越來越流行而且變演一個重要的角色。基於這個理由，我們需要最佳化的嵌入式數位訊號處理器編譯器來產生對性能、功率消耗、面積和生產力而言是有效率的程式碼。由於可以增加數位訊號處理器特殊硬體的利用率，最佳化的嵌入式數位訊號處理器編譯器可以避免設計師手動調叫應用程式 ─ 這個行為會增加而外的消費並且延長上市的時間。在本論文中，我們開發出一套後處理編譯器框架。它可以由執行時期資訊來最佳化別的編譯器的結果並且增加數位訊號處理器特殊硬體的利用率。在實驗的結果，我們可以看到本框架可以最佳化Blackfin GCC 3.4和VDSP++ 4.5所產生的執行檔並且得到平均17.56%和8.8%的效能改進。除此之外，本框架還能最佳化被手寫函式庫最佳化過的真實多媒體程式H.264並且得到5.8%的效能改進。

關鍵字

超長指令集編譯器最佳化 ； 數位訊號處理器編譯器最佳化

並列摘要

In the high performance and low power multimedia embedded system design, the VLIW-based embedded DSPs which need compiler to exploit the ILP become popular and play an important role today. For this reason, we need optimizing embedded DSP compilers that can generate capable code with efficiency in terms of performance, power, area, and productivity in order to use embedded DSPs effectively. With exploiting the specific hardware feature of DSPs, the embedded DSP compilers can avoid designer to optimize applications on hand which will increase the time-to-market without lost performance. In this paper, we show that using the proposed post compilation framework, we can exploit hardware specific features of DSPs with runtime information to optimize the results of other compilers. In the simulation results, we demonstrate that the proposed framework can optimize the programs optimized by another compiler Blackfin GCC 3.4 and VDSP++ 4.5 with optimization level 3 and get additional 17.56% and 8.8% performance on average. We also can get additional 5.8% performance on average of the real multimedia program H.264 which is optimized by hand-turned DSP library.

參考文獻

[3] D.F. Bacon, S.L. Graham and O.J. Sharp. “Compiler Transformations for High-Performance Computing.”, ACM Computing Surveys, Dec. 1994.

[5] H. Falk, “Control Flow Optimization by Loop Nest Splitting at the Source Code Level”, Research Report No 773, Oct. 2002.

[8] The GCC - the gnu compiler collection, http://gcc.gnu.org/ , 1987

[11] J.L. Hennessy and D.A. Patterson, “Computer Architecture: A quantitative approach 4th Edition”, Morgan Kaufmann, 2006.

[12] C.E. Kozyrakis and D.A. Patterson, “Scalable Vector Processors for Embedded Systems”, IEEE Computer Society, 2003.